EP4CE55F23C9LN Altera, EP4CE55F23C9LN Datasheet - Page 177

• Manufacturer Part Number: EP4CE55F23C9LN
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C9LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
© December 2010 Altera Corporation
1
Figure 8–2. Single-Device AS Configuration
Notes to
(1) Connect the pull-up resistors to the V
(2) Cyclone IV devices use the ASDO-to-ASDI path to control the configuration device.
(3) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect the MSEL pins,
(5) Connect the series resistor at the near end of the serial configuration device.
(6) These pins are dual-purpose I/O pins. The nCSO pin functions as FLASH_nCE pin in AP mode. The ASDO pin
(7) Only Cyclone IV GX devices have an option to select CLKUSR (40 MHz maximum) as the external clock source for
The 25- resistor at the near end of the serial configuration device for DATA[0] works
to minimize the driver impedance mismatch with the board trace and reduce the
overshoot seen at the Cyclone IV device DATA[0] input pin.
In the single-device AS configuration, the maximum board loading and board trace
length between the supported serial configuration device and the Cyclone IV device
must follow the recommendations in
The DCLK generated by the Cyclone IV device controls the entire configuration cycle
and provides timing for the serial interface. Cyclone IV devices use an internal
oscillator or an external clock source to generate the DCLK. For Cyclone IV E devices,
you can use a 40-MHz internal oscillator to generate the DCLK and for Cyclone IV GX
devices you can use a slow clock (20 MHz maximum) or a fast clock
(40 MHz maximum) from the internal oscillator or an external clock from CLKUSR to
generate the DCLK. There are some variations in the internal oscillator frequency
because of the process, voltage, and temperature (PVT) conditions in Cyclone IV
devices. The internal oscillator is designed to ensure that its maximum frequency is
guaranteed to meet EPCS device specifications. Cyclone IV devices offer the option to
select CLKUSR as the external clock source for DCLK. You can change the clock source
option in the Quartus II software in the Configuration tab of the Device and Pin
Options dialog box.
refer to
to V
functions as the DATA[1] pin in AP and FPP modes.
DCLK.
Serial Configuration
CCA
Figure
or GND.
Table 8–3 on page
Device
8–2:
DCLK
DATA
ASDI
nCS
10 kΩ
V
CCIO
8–8,
25 Ω (5)
(1)
Table 8–4 on page
10 kΩ
V
CCIO
CCIO
(2)
supply of the bank in which the pin resides.
(1)
10 kΩ
Table 8–6 on page
V
GND
8–8, and
CCIO
(1)
Table 8–5 on page
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA[0]
DCLK
nCSO (6)
ASDO (6)
Cyclone IV Device
8–17.
Cyclone IV Device Handbook, Volume 1
8–9. Connect the MSEL pins directly
CLKUSR
MSEL[ ]
nCEO
N.C. (3)
(7)
(4)
8–11