EP4CE55F23C9LN Altera, EP4CE55F23C9LN Datasheet - Page 394

• Manufacturer Part Number: EP4CE55F23C9LN
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C9LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

3–4
Table 3–2. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 2 of 6)
Cyclone IV Device Handbook, Volume 2
FPGA Fabric and ALTGX_RECONFIG Interface Signals
write_all
busy
read
data_valid
error
logical_channel_
address[n..0]
Port Name
Output
Output
Output
Output
Input/
Input
Input
Input
Assert this signal for one reconfig_clk clock cycle to initiate a write transaction from the
ALTGX_RECONFIG instance to the ALTGX instance.
You can use this signal in two ways for .mif-based modes:
■
■
This signal is used to indicate the busy status of the dynamic reconfiguration controller during
offset cancellation. After the device powers up, this signal remains low for the first
reconfig_clk clock cycle. It then is asserted and remains high when the dynamic
reconfiguration controller performs offset cancellation on all the receiver channels connected to
the ALTGX_RECONFIG instance.
Deassertion of the busy signal indicates the successful completion of the offset cancellation
process.
■
■
Assert this signal for one reconfig_clk clock cycle to initiate a read transaction. The read
port is applicable only to the PMA controls reconfiguration mode. The read port is available
when you select Analog controls in the Reconfiguration settings screen and select at least one
of the PMA control ports in the Analog controls screen.
Applicable only to PMA controls reconfiguration mode. This port indicates the validity of the
data read from the transceiver by the dynamic reconfiguration controller.
The data on the output read ports is valid only when the data_valid is high.
This signal is enabled when you enable at least one PMA control port used in read transactions,
for example tx_vodctrl_out.
This indicates that an unsupported operation was attempted. You can select this in the Error
checks screen. The dynamic reconfiguration controller deasserts the busy signal and asserts
the error signal for two reconfig_clk cycles when you attempt an unsupported
operation. For more information, refer to
page
Enabled by the ALTGX_RECONFIG MegaWizard Plug-In Manager when you enable the Use
'logical_channel_address' port for Analog controls reconfiguration option in the Analog
controls screen.
The width of the logical_channel_address port depends on the value you set in the
What is the number of channels controlled by the reconfig controller? option in the
Reconfiguration settings screen. This port can be enabled only when the number of channels
controlled by the dynamic reconfiguration controller is more than one.
Number of channels controlled
by the reconfiguration controller
2
3–4
5–8
9–16
Continuous write operation—select the Enable continuous write of all the words needed for
reconfiguration option to pulse the write_all signal only once for writing a whole .mif.
The What is the read latency of the MIF contents option is available for selection in this case
only. Enter the desired latency in terms of the reconfig_clk cycles.
Regular write operation—when the Enable continuous write of all the words needed for
reconfiguration option is disabled, every word of the .mif requires its own write cycle.
PMA controls reconfiguration mode—this signal is high when the dynamic reconfiguration
controller performs a read or write transaction.
Channel reconfiguration modes—this signal is high when the dynamic reconfiguration
controller writes the .mif into the transceiver channel.
3–33.
“Error Indication During Dynamic Reconfiguration” on
Description
Chapter 3: Cyclone IV Dynamic Reconfiguration
logical_channel_address[0]
logical_channel_address[1..0]
logical_channel_address[2..0]
logical_channel_address[3..0]
logical_channel_address
input port width
Dynamic Reconfiguration Controller Port List
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