EP4CE55F23C9LN Altera, EP4CE55F23C9LN Datasheet - Page 225

• Manufacturer Part Number: EP4CE55F23C9LN
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C9LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
© December 2010 Altera Corporation
1
ACTIVE_ENGAGE
The ACTIVE_ENGAGE instruction allows you to re-engage a disengaged active
controller. You can issue this instruction any time during configuration or user mode
to re-engage an already disengaged active controller, as well as trigger
reconfiguration of the Cyclone IV device in the active configuration scheme.
The ACTIVE_ENGAGE instruction functions as the PULSE_NCONFIG instruction when
the device is in the PS or FPP configuration schemes. The nCONFIG pin is disabled
when the ACTIVE_ENGAGE instruction is issued.
Altera does not recommend using the ACTIVE_ENGAGE instruction, but it is provided
as a fail-safe instruction for re-engaging the active configuration controller (AS and
AP).
Overriding the Internal Oscillator
This feature allows you to override the internal oscillator during the active
configuration scheme. The AS and AP configuration controllers use the internal
oscillator as the clock source. You can change the clock source to CLKUSR through the
JTAG instruction.
The EN_ACTIVE_CLK and DIS_ACTIVE_CLK JTAG instructions toggle on or off
whether or not the active clock is sourced from the CLKUSR pin or the internal
configuration oscillator. To source the active clock from the CLKUSR pin, issue the
EN_ACTIVE_CLK instruction. This causes the CLKUSR pin to become the active clock
source. When using the EN_ACTIVE_CLK instruction, you must enable the internal
oscillator for the clock change to occur. By default, the configuration oscillator is
disabled after configuration and initialization is complete as well as the device has
entered user mode.
However, the internal oscillator is enabled in user mode by any of the following
conditions:
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■
■
You must clock the CLKUSR pin at two times the expected DCLK frequency. The
CLKUSR pin allows a maximum frequency of 80 MHz (40 MHz DCLK). Normally, a
test instrument uses the CLKUSR pin when it wants to drive its own clock to control
the AS state machine.
To revert the clock source back to the configuration oscillator, issue the
DIS_ACTIVE_CLK instruction. After you issue the DIS_ACTIVE_CLK instruction,
you must continue to clock the CLKUSR pin for 10 clock cycles. Otherwise, even
toggling the nCONFIG pin does not revert the clock source and reconfiguration does
not occur. A POR reverts the clock source back to the configuration oscillator.
Toggling the nCONFIG pin or driving the JTAG state machine to reset state does not
revert the clock source.
A reconfiguration event (for example, driving the nCONFIG pin to go low)
Remote update is enabled
Error detection is enabled
Cyclone IV Device Handbook, Volume 1
8–59