EP4CE55F23C9LN Altera, EP4CE55F23C9LN Datasheet - Page 18

• Manufacturer Part Number: EP4CE55F23C9LN
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C9LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–4
Table 1–2. Resources for the Cyclone IV GX Device Family
Cyclone IV Device Handbook, Volume 1
Logic elements (LEs)
Embedded memory (Kbits)
Embedded 18 × 18 multipliers
General purpose PLLs
Multipurpose PLLs
Global clock networks
High-speed transceivers
Transceiver maximum data rate
(Gbps)
PCIe (PIPE) hard IP blocks
User I/O banks
Maximum user I/O
Notes to
(1) Applicable for the F169 and F324 packages.
(2) Applicable for the F484 package.
(3) Only two multipurpose PLLs for F484 package.
(4) Two of the general purpose PLLs are able to support transceiver clocking. For more information, refer to the
(5) You can use the multipurpose PLLs for general purpose clocking when they are not used to clock the transceivers. For more information, refer to
(6) If PCIe 1, you can use the remaining transceivers in a quad for other protocols at the same or different data rates.
(7) Including one configuration I/O bank and two dedicated clock input I/O banks for HSSI reference clock input.
(8) Including one configuration I/O bank and four dedicated clock input I/O banks for HSSI reference clock input.
(9) The user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiver
Cyclone IV Devices
the
pins and dedicated configuration pins are not included in the pin count.
Clock Networks and PLLs in Cyclone IV Devices
Table
Resources
1–2:
(9)
chapter.
Table 1–2
(6)
lists Cyclone IV GX device resources.
14,400
2
9
540
2.5
20
72
0
1
2
1
(5)
(7)
21,280
2
9
756
150
chapter.
2.5
40
20
2
4
1
(5)
(7)
29,440
1,080
2
9
150
2.5
20
80
2
(5)
4
1
(7)
29,440
11
1,080
3.125
4
2
290
80
30
(4)
(5)
4
1
(8)
Chapter 1: Cyclone IV FPGA Device Family Overview
49,888
11
2,502
3.125
4
4
140
310
30
8
1
(4)
(5)
(8)
© December 2010 Altera Corporation
73,920
11
4,158
3.125
4
4
198
310
30
Clock Networks and PLLs in
8
1
(4)
(5)
(8)
109,424
11
5,490
3.125
4
4
280
475
30
8
1
(4)
(5)
(8)
Device Resources
149,760
11
6,480
3.125
4
4
360
475
30
(4)
(5)
8
1
(8)