EP4CE55F23C9LN Altera, EP4CE55F23C9LN Datasheet - Page 97

• Manufacturer Part Number: EP4CE55F23C9LN
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C9LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
PLL Reconfiguration
PLL Reconfiguration
PLL Reconfiguration Hardware Implementation
© December 2010 Altera Corporation
PLLs use several divide counters and different VCO phase taps to perform frequency
synthesis and phase shifts. In PLLs of Cyclone IV devices, you can reconfigure both
counter settings and phase shift the PLL output clock in real time. You can also change
the charge pump and loop filter components, which dynamically affects PLL
bandwidth. You can use these PLL components to update the output clock frequency,
PLL bandwidth, and phase shift in real time, without reconfiguring the entire FPGA.
The ability to reconfigure the PLL in real time is useful in applications that might
operate at multiple frequencies. It is also useful in prototyping environments,
allowing you to sweep PLL output frequencies and adjust the output clock phase
dynamically. For instance, a system generating test patterns is required to generate
and send patterns at 75 or 150 MHz, depending on the requirements of the device
under test. Reconfiguring PLL components in real time allows you to switch between
two such output frequencies in a few microseconds.
You can also use this feature to adjust clock-to-out (t
changing the PLL output clock phase shift. This approach eliminates the need to
regenerate a configuration file with the new PLL settings.
The following PLL components are configurable in real time:
■
■
■
■
Figure 5–22
new settings into a serial shift register chain or scan chain. Serial data shifts to the scan
chain via the scandataport, and shift registers are clocked by scanclk. The
maximum scanclk frequency is 100 MHz. After shifting the last bit of data, asserting
the configupdate signal for at least one scanclk clock cycle synchronously
updates the PLL configuration bits with the data in the scan registers.
Pre-scale counter (N)
Feedback counter (M)
Post-scale output counters (C0–C4)
Dynamically adjust the charge pump current (I
(R, C) to facilitate on-the-fly reconfiguration of the PLL bandwidth
shows how to adjust PLL counter settings dynamically by shifting their
CP
) and loop filter components
CO
) delays in real time by
Cyclone IV Device Handbook, Volume 1
5–35