EP4CE55F23C9LN Altera, EP4CE55F23C9LN Datasheet - Page 232

• Manufacturer Part Number: EP4CE55F23C9LN
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C9LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

8–66
Table 8–18. Dedicated Configuration Pins on the Cyclone IV Device (Part 4 of 4)
Cyclone IV Device Handbook, Volume 1
DATA[7..2]
DATA[15..8]
PADD[23..0]
nRESET
nAVD
nOE
nWE
Note to
(1) The AP configuration scheme is for Cyclone IV E devices only.
Pin Name
Table
8–18:
Mode
User
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Configuration
FPP, AP
Scheme
AP
AP
AP
AP
AP
AP
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Bidirectional
Bidirectional
Pin Type
(AP)
Output
Output
Output
Output
Output
Inputs
(FPP).
(1)
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
In an AS or PS configuration scheme, DATA[7..2] function
as user I/O pins during configuration, which means they are
tri-stated.
After FPP configuration, DATA[7..2] are available as user I/O
pins and the state of these pin depends on the Dual-Purpose
Pin settings.
In an AP configuration scheme, for Cyclone IV E devices only,
the byte-wide or word-wide configuration data is presented to
the target Cyclone IV E device on DATA[7..0] or
DATA[15..0], respectively. After AP configuration,
DATA[7..2]are dedicated bidirectional pins with optional
user control.
Data inputs. Word-wide configuration data is presented to the
target Cyclone IV E device on DATA[15..0].
In a PS, FPP, or AS configuration scheme, DATA[15:8]
function as user I/O pins during configuration, which means
they are tri stated.
After AP configuration, DATA[15:8]are dedicated
bidirectional pins with optional user control.
In AP mode, it is a 24-bit address bus from the Cyclone IV E
device to the parallel flash. Connects to the A[24:1]bus on
the Numonyx P30 or P33 flash.
Active-low reset output. Driving the nRESET pin low resets the
parallel flash. Connects to the RST# pin on the Numonyx P30 or
P33 flash.
Active-low address valid output. Driving the nAVD pin low
during read or write operation indicates to the parallel flash that
a valid address is present on the PADD[23..0]address bus.
Connects to the ADV# pin on the Numonyx P30 or P33 flash.
Active-low output enable to the parallel flash. During the read
operation, driving the nOE pin low enables the parallel flash
outputs (DATA[15..0]). Connects to the OE# pin on the
Numonyx P30 or P33 flash.
Active-low write enable to the parallel flash. During the write
operation, driving the nWE pin low indicates to the parallel flash
that data on the DATA[15..0]bus is valid. Connects to the
WE# pin on the Numonyx P30 or P33 flash.
(1)
Description
© December 2010 Altera Corporation
Configuration