EP4CE55F23C9LN Altera, EP4CE55F23C9LN Datasheet - Page 198

• Manufacturer Part Number: EP4CE55F23C9LN
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C9LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

8–32
Cyclone IV Device Handbook, Volume 1
1
PS Configuration Using an External Host
In the PS configuration scheme, you can use an intelligent host such as a MAX II
device or microprocessor that controls the transfer of configuration data from a
storage device, such as flash memory, to the target Cyclone IV device. You can store
the configuration data in .rbf, .hex, or .ttf format.
Figure 8–13
device and an external host device for single-device configuration.
Figure 8–13. Single-Device PS Configuration Using an External Host
Notes to
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for the device. V
(2) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect the MSEL pins,
(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[0] and DCLK must fit the maximum overshoot
To begin the configuration, the external host device must generate a low-to-high
transition on the nCONFIG pin. When nSTATUS is pulled high, the external host
device must place the configuration data one bit at a time on DATA[0]. If you use
configuration data in .rbf, .ttf, or .hex, you must first send the LSB of each data byte.
For example, if the .rbf contains the byte sequence 02 1B EE 01 FA, the serial bitstream
you must send to the device is:
Cyclone IV devices receive configuration data on DATA[0] and the clock is received
on DCLK. Data is latched into the device on the rising edge of DCLK. Data is
continuously clocked into the target device until CONF_DONE goes high and the
device enters initialization state.
Two DCLK falling edges are required after CONF_DONE goes high to begin the
initialization of the device.
INIT_DONE is released and pulled high when initialization is complete. The external
host device must be able to detect this low-to-high transition which signals the device
has entered user mode. When initialization is complete, the device enters user mode.
In user mode, the user I/O pins no longer have weak pull-up resistors and function as
assigned in your design.
enough to meet the V
refer to
to V
outlined in
CCA
Figure
0100-0000 1101-1000 0111-0111 1000-0000 0101-1111
or GND.
Table 8–3 on page
Equation 8–1 on page
shows the configuration interface connections between a Cyclone IV
8–13:
(MAX II Device or
Microprocessor)
External Host
IH
specification of the I/O on the device and the external host.
ADDR
8–8,
Memory
Table 8–4 on page
DATA[0]
8–5.
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
10 kΩ
V
CCIO
(1) V
8–8, and
10 kΩ
GND
CCIO
(1)
Table 8–5 on page
CONF_DONE
nSTATUS
nCE
DATA[0] (4)
nCONFIG
DCLK (4)
Cyclone IV
Device
MSEL[ ]
nCEO
© December 2010 Altera Corporation
8–9. Connect the MSEL pins directly
N.C. (2)
(3)
CC
must be high
Configuration