EP4CE55F23C9LN Altera, EP4CE55F23C9LN Datasheet - Page 398

• Manufacturer Part Number: EP4CE55F23C9LN
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C9LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

3–8
Table 3–2. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 6 of 6)
Cyclone IV Device Handbook, Volume 2
reconfig_address
_out[5..0]
reconfig_address
_en
reset_reconfig_
address
reconfig_data
[15..0]
reconfig_reset
channel_reconfig
_done
Notes to
(1) Not all combinations of input bits are legal values.
(2) This setting is required for compliance to PCI Express
(3) PLL reconfiguration is performed using ALTPLL_RECONFIG controller. Hence it is not selected through the
(4) reconfig_reset will not restart the offset cancellation operation. Offset cancellation only occurs one time after power up and
reconfig_mode_sel[2..0] port.
does not occur when subsequent reconfig_reset is asserted.
Port Name
Table
3–2:
(4)
Output
Output
Output
Output
Input/
Input
Input
Input
This signal is always available for you to select in the Channel reconfiguration screen. This
signal is applicable only in the dynamic reconfiguration modes grouped under Channel
reconfiguration mode including channel interface and Use RX local divider option.
This signal represents the current address used by the ALTGX_RECONFIG instance when
writing the .mif into the transceiver channel. This signal increments by 1, from 0 to the last
address, then starts at 0 again. You can use this signal to indicate the end of all the .mif write
transactions (reconfig_address_out[5..0] changes from the last address to 0 at the
end of all the .mif write transactions).
This is an optional signal you can select in the Channel reconfiguration screen. This signal is
applicable only in dynamic reconfiguration modes grouped under the Channel reconfiguration
option.
The dynamic reconfiguration controller asserts reconfig_address_en to indicate that
reconfig_address_out[5..0] has changed. This signal is asserted only after the
dynamic reconfiguration controller completes writing one 16-bit word of the .mif.
This is an optional signal you can select in the Channel reconfiguration screen. This signal is
applicable only in dynamic reconfiguration modes grouped under the Channel reconfiguration
option.
Enable this signal and assert it for one reconfig_clk clock cycle if you want to reset the
reconfiguration address used by the ALTGX_RECONFIG instance during reconfiguration.
This signal is applicable only in the dynamic reconfiguration modes grouped under the Channel
reconfiguration option. This is a 16-bit word carrying the reconfiguration information. It is
stored in a .mif that you must generate. The ALTGX_RECONFIG instance requires that you
provide reconfig_data [15..0]on every .mif write transaction using the write_all
signal.
You can use this signal to reset all the reconfiguration process in Channel reconfiguration
mode. Asserting this port will reset all the register in the reconfiguration controller logics. This
port only shows up in Channel reconfiguration mode.
This signal goes high to indicate that the dynamic reconfiguration controller has finished writing
all the words of the .mif. The channel_reconfig_done signal is automatically deasserted
at the start of a new dynamic reconfiguration write sequence. This signal is applicable only in
channel reconfiguration mode.
®
(PIPE) functional mode.
Description
Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Controller Port List
© December 2010 Altera Corporation