EP4CE55F23C9LN Altera, EP4CE55F23C9LN Datasheet - Page 217

• Manufacturer Part Number: EP4CE55F23C9LN
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C9LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
© December 2010 Altera Corporation
f
f
1
JTAG configuration allows an unlimited number of Cyclone IV devices to be cascaded
in a JTAG chain.
For more information about configuring multiple Altera devices in the same
configuration chain, refer to the
volume 2 of the Configuration Handbook.
Figure 8–27
microprocessor.
Figure 8–27. JTAG Configuration of a Single Device Using a Microprocessor
Notes to
(1) You must connect the pull-up resistor to a supply that provides an acceptable input signal for all devices in the chain.
(2) Connect the nCONFIG and MSEL pins to support a non-JTAG configuration scheme. If you only use a JTAG
(3) You must connect the nCE pin to GND or driven low for successful JTAG configuration.
(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. Signals driving into TDI, TMS, and TCK must fit the
Configuring Cyclone IV Devices with Jam STAPL
Jam
programmability (ISP) purposes. Jam STAPL supports programming or configuration
of programmable devices and testing of electronic systems, using the IEEE 1149.1
JTAG interface. Jam STAPL is a freely licensed open standard. The Jam Player
provides an interface for manipulating the IEEE Std. 1149.1 JTAG TAP state machine.
For more information about JTAG and Jam STAPL in embedded environments, refer
to
download the Jam Player, visit the Altera website (www.altera.com).
AN 425: Using Command-Line Jam STAPL Solution for Device
configuration, connect the nCONFIG pin to logic-high and the MSEL pins to GND. In addition, pull DCLK and
DATA[0] to either high or low, whichever is convenient on your board.
maximum overshoot outlined in
™
STAPL, JEDEC standard JESD-71, is a standard file format for in-system
Figure
shows JTAG configuration with a Cyclone IV device and a
8–27:
Microprocessor
ADDR
Memory
DATA
Equation 8–1 on page
Configuring Mixed Altera FPGA Chains
N.C.
(2)
(2)
(2)
nCONFIG
DATA[0]
DCLK
TDI (4)
TCK (4)
TMS (4)
nCEO
nCE
Cyclone IV Device
8–5.
(3)
CONF_DONE
nSTATUS
MSEL[ ]
TDO
Cyclone IV Device Handbook, Volume 1
V
(2)
CCIO
Programming. To
10 kΩ
(1)
V
CCIO
10 kΩ
(1)
chapter in
8–51