EP4CE55F23C9LN Altera, EP4CE55F23C9LN Datasheet - Page 397

• Manufacturer Part Number: EP4CE55F23C9LN
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C9LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Controller Port List
Table 3–2. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 5 of 6)
© December 2010 Altera Corporation
rx_eqdcgain
[1..0]
tx_vodctrl_out
[2..0]
tx_preemp_out
[4..0]
rx_eqctrl_out
[3..0]
rx_eqdcgain_out
[1..0]
Transceiver Channel Reconfiguration Control/Status Signals
reconfig_mode_
sel[2..0](3)
Port Name
(1)
Output
Output
Output
Output
Output
Input/
Input
Input
This is an optional equalizer DC gain write control.
The width of this signal is fixed to 2 bits if you enable either the Use 'logical_channel_address'
port for Analog controls reconfiguration option or the Use same control signal for all the
channels option in the Analog controls screen. Otherwise, the width of this signal is 2 bits per
channel.
The following values are the legal settings allowed for this signal:
rx_eqdcgain[1..0]
2’b00
2’b01
2’b11
All other values => N/A
For more information, refer to the “Programmable Equalization and DC Gain” section of the
Cyclone IV GX Device Datasheet
This is an optional transmit V
the V
controlled by the dynamic reconfiguration controller and also the configuration of the Use
'logical_channel_address' port for Analog controls reconfiguration option and the Use same
control signal for all the channels option.
This is an optional pre-emphasis read control signal. This signal reads out the value written by
its input control signal. The width of this output signal depends on the number of channels
controlled by the dynamic reconfiguration controller and also the configuration of the Use
'logical_channel_address' port for Analog controls reconfiguration option and the Use same
control signal for all the channels option.
This is an optional read control signal to read the setting of equalization setting of the ALTGX
instance. The width of this output signal depends on the number of channels controlled by the
dynamic reconfiguration controller and also the configuration of the Use
'logical_channel_address' port for Analog controls reconfiguration option and the Use same
control signal for all the channels option.
This is an optional equalizer DC gain read control signal. This signal reads out the settings of the
ALTGX instance DC gain. The width of this output signal depends on the number of channels
controlled by the dynamic reconfiguration controller and also the configuration of the Use
'logical_channel_address' port for Analog controls reconfiguration option and the Use same
control signal for all the channels option.
Set the following values at this signal to activate the appropriate dynamic reconfiguration mode:
3’b000 = PMA controls reconfiguration mode. This is the default value.
3’b001 = Channel reconfiguration mode
All other values => N/A
reconfig_mode_sel[] is available as an input only when you enable more than one
dynamic reconfiguration mode.
OD
control register. The width of this output signal depends on the number of channels
OD
Corresponding ALTGX
read control signal. This signal reads out the value written into
chapter.
settings
0
1
2
Description
Cyclone IV Device Handbook, Volume 2
DC Gain value (dB)
Corresponding
0
3
6
(2)
3–7