EP4CE55F23C9LN Altera, EP4CE55F23C9LN Datasheet - Page 63

• Manufacturer Part Number: EP4CE55F23C9LN
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C9LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Clock Networks
© December 2010 Altera Corporation
CYIV-51005-2.2
f
1
This chapter describes the hierarchical clock networks and phase-locked loops (PLLs)
with advanced features in the Cyclone
ability to reconfigure the PLL counter clock frequency and phase shift in real time,
allowing you to sweep PLL output frequencies and dynamically adjust the output
clock phase shift.
The Quartus
This chapter contains the following sections:
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The Cyclone IV GX device provides up to 12 dedicated clock pins (CLK[15..4]) that
can drive the global clocks (GCLKs). Cyclone IV GX devices support four dedicated
clock pins on each side of the device except the left side. These clock pins can drive up
to 30 GCLKs.
The Cyclone IV E device provides up to 15 dedicated clock pins (CLK[15..1]) that
can drive up to 20 GCLKs. Cyclone IV E devices support three dedicated clock pins
on the left side and four dedicated clock pins on the top, right, and bottom sides of the
device except EP4CE6 and EP4CE10 devices. EP4CE6 and EP4CE10 devices only
support three dedicated clock pins on the left side and four dedicated clock pins on
the right side of the device.
For more information about the number of GCLK networks in each device density,
refer to the
“Clock Networks” on page 5–1
“PLLs in Cyclone IV Devices” on page 5–16
“Cyclone IV PLL Hardware Overview” on page 5–19
“Clock Feedback Modes” on page 5–22
“Hardware Features” on page 5–26
“Programmable Bandwidth” on page 5–32
“Phase Shift Implementation” on page 5–32
“PLL Cascading” on page 5–34
“PLL Reconfiguration” on page 5–35
“Spread-Spectrum Clocking” on page 5–43
“PLL Specifications” on page 5–43
Cyclone IV FPGA Device Family Overview
®
II software enables the PLLs and their features without external devices.
5. Clock Networks and PLLs in
®
IV device family. It includes details about the
chapter.
Cyclone IV Devices
Cyclone IV Device Handbook, Volume 1