EP4CE55F23C9LN Altera, EP4CE55F23C9LN Datasheet - Page 359

• Manufacturer Part Number: EP4CE55F23C9LN
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C9LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Top-Level Port Lists
Transceiver Top-Level Port Lists
Table 1–26. Transmitter Ports in ALTGX Megafunction for Cyclone IV GX
© December 2010 Altera Corporation
TX PCS
TX PMA
Block
tx_datain
tx_clkout
tx_coreclk
tx_phase_comp_
fifo_error
tx_ctrlenable
tx_forcedisp
tx_dispval
tx_invpolarity
tx_bitslipboun
daryselect
tx_dataout
tx_forceelec
idle
Port Name
Table 1–26
instantiating a transceiver using the ALTGX megafunction. The ALTGX megafunction
requires a relatively small number of signals. There are also a large number of
optional signals that facilitate debugging by providing information about the state of
the transceiver.
Output
Output Clock signal
Output
Output
Input/
Input
Input
Input
Input
Input
Input
Input
Input
through
Synchronous to
tx_clkout (non-bonded
modes) or coreclkout
(bonded modes)
Clock signal
Synchronous to
tx_clkout (non-bonded
modes) or coreclkout
(bonded modes)
Synchronous to
tx_clkout (non-bonded
modes) or coreclkout
(bonded modes)
Synchronous to
tx_clkout (non-bonded
modes) or coreclkout
(bonded modes)
Synchronous to
tx_clkout (non-bonded
modes) or coreclkout
(bonded modes)
Asynchronous signal.
Minimum pulse width is two
parallel clock cycles.
Asynchronous signal.
Asynchronous signal.
Table 1–29
Clock Domain
—
provide descriptions of the ports available when
Parallel data input from the FPGA fabric to the transmitter.
■
FPGA fabric-transmitter interface clock in non-bonded modes
■
Optional write clock port for the TX phase compensation FIFO.
TX phase compensation FIFO full or empty indicator.
■
8B/10B encoder control or data identifier. This signal passes
through the TX Phase Compensation FIFO.
■
■
8B/10B encoder forcing disparity control. This signal passes
through the TX Phase Compensation FIFO.
■
■
8B/10B encoder forcing disparity value. This signal passes
through the TX Phase Compensation FIFO.
■
■
Transmitter polarity inversion control.
■
Control the number of bits to slip before serializer.
■
Transmitter serial data output signal.
Force the transmitter buffer to PIPE electrical idle signal levels.
For equivalent signal defined in PIPE 2.00 specification, refer to
Table 1–15 on page
Bus width depends on channel width multiplied by number
of channels per instance.
Each channel has a tx_clkout signal that can be used to
clock data (tx_datain) from the FPGA fabric into the
transmitter.
A high level indicates FIFO is either full or empty.
A high level to encode data as a /Kx.y/ control code group.
A low level to encode data as a /Dx.y/ data code group.
A high level to force encoding to positive or negative
disparity depending on the tx_dispval signal level.
A low level to allow default encoding according to the
8B/10B running disparity rules.
A high level to force encoding with a negative disparity code
group when tx_forcedisp port is asserted high.
A low level to force encoding with a positive disparity code
group when tx_forcedisp port is asserted high.
A high level to invert the polarity of every bit of the 8- or 10-
bit input data to the serializer.
Valid values from 0 to 9
Cyclone IV Device Handbook, Volume 2
1–50.
Description
1–79