EP4CE55F23C9LN Altera, EP4CE55F23C9LN Datasheet - Page 411

• Manufacturer Part Number: EP4CE55F23C9LN
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C9LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Modes
Table 3–4. tx_datainfull[21..0] FPGA Fabric-Transceiver Channel Interface Signal Descriptions
© December 2010 Altera Corporation
FPGA Fabric-Transceiver Channel
Interface Description
8-bit FPGA fabric-Transceiver Channel
Interface
10-bit FPGA fabric-Transceiver Channel
Interface
16-bit FPGA fabric-Transceiver Channel
Interface with PCS-PMA set to 8/10 bits
20-bit FPGA fabric-Transceiver Channel
Interface with PCS-PMA set to 10 bits
Note to
(1) For all transceiver-related ports, refer to the “Transceiver Port Lists” section in the
Table
3–4:
Table 3–4
interface signals.
describes the tx_datainfull[21..0] FPGA fabric-transceiver channel
Transmit Signal Description (Based on Cyclone IV GX Supported FPGA
Fabric-Transceiver Channel Interface Widths)
tx_datainfull[7:0]: 8-bit data (tx_datain)
The following signals are used only in 8B/10B modes:
tx_datainfull[8]: Control bit (tx_ctrlenable)
tx_datainfull[9]
Transmitter force disparity Compliance (PCI Express [PIPE]) (tx_forcedisp) in all
modes except PCI Express (PIPE) functional mode. For PCI Express (PIPE) functional
mode, (tx_forcedispcompliance) is used.
tx_datainfull[10]: Forced disparity value (tx_dispval)
tx_datainfull[9:0]: 10-bit data (tx_datain)
Two 8-bit Data (tx_datain)
tx_datainfull[7:0] - tx_datain (LSByte) and
tx_datainfull[18:11] - tx_datain (MSByte)
The following signals are used only in 8B/10B modes:
tx_datainfull[8] - tx_ctrlenable (LSB) and tx_datainfull[19] -
tx_ctrlenable (MSB)
Force Disparity Enable
tx_datainfull[9] - tx_forcedisp (LSB) and tx_datainfull[20] -
tx_forcedisp (MSB)
Force Disparity Value
tx_datainfull[10] - tx_dispval (LSB) and tx_datainfull[21] -
tx_dispval (MSB)
Two 10-bit Data (tx_datain)
tx_datainfull[9:0] - tx_datain (LSByte) and
tx_datainfull[20:11] - tx_datain (MSByte)
Cyclone IV GX Transceiver Architecture
Cyclone IV Device Handbook, Volume 2
(Note 1)
chapter.
3–21