EP4CE55F23C9LN Altera, EP4CE55F23C9LN Datasheet - Page 416

• Manufacturer Part Number: EP4CE55F23C9LN
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C9LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

3–26
Cyclone IV Device Handbook, Volume 2
Table 3–6
mode in Cyclone IV GX devices.
Table 3–6. Dynamic Reconfiguration Clocking Interface Settings in Channel Reconfiguration Mode
Transmitter core clocking refers to the clock that is used to write the parallel data from
the FPGA fabric into the Transmit Phase Compensation FIFO. You can use one of the
following clocks to write into the Transmit Phase Compensation FIFO:
■
■
Option 1: Share a Single Transmitter Core Clock Between Transmitters
■
■
Dynamic Reconfiguration Channel Internal and Interface Settings
How should the receivers be
clocked?
How should the transmitters be
clocked?
tx_coreclk—you can use a clock of the same frequency as tx_clkout from the
FPGA fabric to provide the write clock to the Transmit Phase Compensation FIFO.
If you use tx_coreclk, it overrides the tx_clkout options in the ALTGX
MegaWizard Plug-In Manager.
tx_clkout—the Quartus II software automatically routes tx_clkout to the
FPGA fabric and back into the Transmit Phase Compensation FIFO.
Enable this option if you want tx_clkout of the first channel (channel 0) of the
transceiver block to provide the write clock to the Transmitter Phase
Compensation FIFOs of the remaining channels in the transceiver block.
This option is typically enabled when all the channels of a transceiver block have
the same functional mode and data rate and are reconfigured to the identical
functional mode and data rate.
ALTGX Setting
lists the supported clocking interface settings for channel reconfiguration
Select one of the available options:
■
■
■
Select one of the available options:
■
■
Share a single transmitter core clock between receivers
Use the respective channel transmitter core clocks
Use the respective channel receiver core clocks
Share a single transmitter core clock between transmitters
Use the respective channel transmitter core clocks
Chapter 3: Cyclone IV Dynamic Reconfiguration
Description
© December 2010 Altera Corporation
Dynamic Reconfiguration Modes