EP4CE55F23C9LN Altera, EP4CE55F23C9LN Datasheet - Page 422

• Manufacturer Part Number: EP4CE55F23C9LN
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C9LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

3–32
Figure 3–16. ALTGX and ALTPLL_RECONFIG Connection for PLL Reconfiguration Mode
Notes to
(1) <n> = (number of transceiver PLLs configured in the ALTGX MegaWizard) - 1.
(2) You must connect the pll_reconfig_done signal from the ALTGX to the pll_scandone port from ALTPLL_RECONFIG.
(3) You need two ALTPLL_RECONFIG controllers if you have two separate ALTGX instances with transceiver PLL instantiated in each ALTGX instance.
Cyclone IV Device Handbook, Volume 2
Table 3–7. ALTGX Megafunction Port List for PLL Reconfiguration Mode (Part 1 of 2)
pll_areset [n..0]
pll_scandata
[n..0]
To external
ROM
Port Name
Figure
rom_address_out[7..0]
f
3–16:
write_rom_ena
(1)
rom_data_in
Figure 3–16
For more information about connecting the ALTPLL_RECONFIG and ALTGX
instances, refer to the
Devices.
Table 3–7
Output
Input/
Input
Input
ALTPLL_RECONFIG (3)
lists the ALTGX megafunction ports for PLL Reconfiguration mode
shows the connection for PLL reconfiguration mode.
Resets the transceiver PLL. The
pll_areset are asserted in two
conditions:
■
■
Receives the scan data input from the
ALTPLL_RECONFIG megafunction.
Used to reset the transceiver PLL
during the reset sequence. During
reset sequence, this signal is user
controlled.
After the transceiver PLL is
reconfigured, this signal is
asserted high by the
ALTPLL_RECONFIG controller. At
this time, this signal is not user
controlled.
PLL_reconfig_done[n..0] (1),(2), pll_scandataout[n..0]
AN 609: Implementing Dynamic Reconfiguration in Cyclone IV GX
Description
PLL_configupdate[n..0]
PLL_scanclkena[n..0]
PLL_scandata[n..0]
PLL_scanclk[n..0]
PLL_areset[n..0]
(1)
(1)
(1)
(1)
(1)
pll_reconfig_signals
You must connect the pll_areset port of ALTGX to the
pll_areset port of the ALTPLL_RECONFIG
megafunction.
The ALTPLL_RECONFIG controller asserts the
pll_areset port at the next rising clock edge after the
pll_reconfig_done signal from the ALTGX
megafunction goes high. After the
pll_reconfig_done signal goes high, the transceiver
PLL is reset. When the PLL reconfiguration is completed,
this reset is performed automatically by the
ALTPLL_RECONFIG megafunction and is not user
controlled.
The reconfigurable transceiver PLL received the scan data
input through this port for the dynamically reconfigurable
bits from the ALTPLL_RECONFIG controller.
Chapter 3: Cyclone IV Dynamic Reconfiguration
(1)
© December 2010 Altera Corporation
Dynamic Reconfiguration Modes
ALTGX
Comments
GXBL0
Transceiver Channels
Transceiver Channels
Transceiver Channels
Transceiver Channels
MPLL2
MPLL1
.