EP4CE55F23C9LN Altera, EP4CE55F23C9LN Datasheet - Page 315

• Manufacturer Part Number: EP4CE55F23C9LN
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C9LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Clocking Architecture
Figure 1–37. Clock Distribution in Bonded (×2 and ×4) Channel Configuration for Transceivers in F324 and Smaller Packages
Notes to
(1) High-speed clock.
(2) Low-speed clock.
(3) Bonded common low-speed clock path.
(4) These PLLs have restricted clock driving capability and may not reach all connected channels. For details, refer to
© December 2010 Altera Corporation
Transceiver
Transceiver
Figure 1–37
GXBL1
GXBL0
Block
Block
Ch3
Ch2
Ch1
Ch0
Ch3
Ch2
Ch1
Ch0
:
2 Bonded Channel Configuration
MPLL_8
MPLL_7
MPLL_6
MPLL_5
(4)
TX PMA
TX PMA
TX PMA
TX PMA
TX PMA
TX PMA
TX PMA
TX PMA
The channel datapath clocking is similar between bonded channels in ×2 and ×4
configurations.
Figure 1–38
bonded configurations. In these configurations, each bonded channel selects the
high-speed clock from one the supported PLLs. The high-speed clock in each bonded
channel feeds the respective serializer for parallel to serial operation. The common
bonded low-speed clock feeds to each bonded channel that is used for the following
blocks in each transmitter PCS channel:
■
■
■
8B/10B encoder
read clock of byte serializer
read clock of TX phase compensation FIFO
(2)
(3)
(3)
(2)
(1)
shows the datapath clocking in Transmitter Only operation for ×2 and ×4
(1)
Not applicable in
F484 package
GPLL_2
GPLL_1
(4)
Transceiver
Transceiver
GXBL1
GXBL0
Block
Block
Ch3
Ch2
Ch1
Ch0
Ch3
Ch2
Ch1
Ch0
4 Bonded Channel Configuration
MPLL_8
MPLL_7
MPLL_6
MPLL_5
TX PMA
TX PMA
TX PMA
TX PMA
TX PMA
TX PMA
TX PMA
TX PMA
(2)
(3)
(3)
(2)
Cyclone IV Device Handbook, Volume 2
(1)
Table
(1)
Not applicable in
1–10.
F484 package
1–35