IDT82V2108PXG IDT, Integrated Device Technology Inc, IDT82V2108PXG Datasheet - Page 133

• Manufacturer Part Number: IDT82V2108PXG
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG

IDT82V2108
Figure 84. Reading Sequence of Indirect Register in T1/
Operation
RWB=1 and address is specified in
Y
the Channel Indirect Address/
Read Channel Indirect Data
J1 Mode
Control Register.
Buffer Register
Set PCCE=1
More data
to be read
BUSY=0
BUSY=0
End
Y
Y
N
N
N
123
4.2.4.5
Control registers can be set as the follows:
- Transmit Clock Slave Mode (System Backplane Rate: 1.544 Mbit/s)
clock. TSCCKA and TSCCKB are both equal to 1.544 M. The N1 (b7~0,
T1/J1-019H) and N2 (b7~0, T1/J1-01AH) are set to their default value
(2FH).
- Transmit Clock Slave Mode (System Backplane Rate: 2.048 Mbit/s)
clock. TSCCKA and TSCCKB are both equal to 2.048 M. The N1 (b7~0,
T1/J1-019H) is set to ‘b11111111 and the N2 (b7~0, T1/J1-01AH) is set
to ‘b11000000.
- Transmit Clock Slave Mode (System Backplane Rate: 4.096 Mbit/s)
CKA is equal to 2.048 M. The N1 (b7~0, T1/J1-019H) is set to
‘b11111111 and the N2 (b7~0, T1/J1-01AH) is set to ‘b11000000.
- Transmit Clock Master Mode
- Transmit Multiplexed Mode (System Backplane Rate: 8.192 Mbit/s)
CKA is equal to 2.048 M. The N1 (b7~0, T1/J1-019H) is set to
‘b11111111 and the N2 (b7~0, T1/J1-01AH) is set to ‘b11000000.
- Transmit Multiplexed Mode (System Backplane Rate: 16.384 Mbit/s)
ence clock. TSCCKA is equal to 2.048 M or 16.384 M. The N1 (b7~0,
T1/J1-019H) is set to ‘b11111111 and the N2 (b7~0, T1/J1-01AH) is set
to ‘b11000000.
In different operation modes, the Timing Options and Clock Divisor
TSCCKA or TSCCKB is selected as the TJAT DPLL input reference
The smoothed clock output from the TJAT is selected as LTCK.
TSCCKA or TSCCKB is selected as the TJAT DPLL input reference
The smoothed clock output from the TJAT is selected as LTCK.
TSCCKA is selected as the TJAT DPLL input reference clock. TSC-
The smoothed clock output from the TJAT is selected as LTCK.
XCK/24 is selected as the TJAT DPLL input reference clock.
XCK/24 is selected as LTCK.
TSCCKA is selected as the TJAT DPLL input reference clock. TSC-
The smoothed clock output from the TJAT is selected as LTCK.
TSCCKA or TSCCKA/8 is selected as the TJAT DPLL input refer-
The smoothed clock output from the TJAT is selected as LTCK.
Using TJAT / Timing Option
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009