IDT82V2108PXG IDT, Integrated Device Technology Inc, IDT82V2108PXG Datasheet - Page 254

• Manufacturer Part Number: IDT82V2108PXG
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG

IDT82V2108
T1 / J1 RCRB Channel Indirect Status (COSS = 0) (041H, 0C1H, 141H, 1C1H, 241H, 2C1H, 341H, 3C1H)
BUSY:
more operations to the indirect registers could be done until this bit is cleared.
T1 / J1 RCRB Channel Indirect Address / Control (COSS = 0) (042H, 0C2H, 142H, 1C2H, 242H, 2C2H, 342H, 3C2H)
R/WB:
A[6:0]:
T1 / J1 RCRB Channel Indirect Data Buffer (COSS = 0) (043H, 0C3H, 143H, 1C3H, 243H, 2C3H, 343H, 3C3H)
isters, the byte to be written must be written into this register before the target indirect register address and R/WB = 0 is written into the Address/Con-
trol register, initiating the access. If data is to be read from the indirect registers, only the target indirect register address and R/WB = 1 is written into
the Address/Control register, initiating the request. After 640 ns, this register will contain the requested data byte.
Programming Information
Bit Name
Bit Name
Bit Name
Default
Default
Default
Bit No.
Bit No.
Bit No.
Type
Type
Type
= 0: No reading or writing operation on the indirect registers is occurring.
= 1: An internal indirect register is being accessed. Any new operation on the internal indirect register is not allowed.
This bit goes low timed to an internal high-speed clock rising edge after the operation has been completed. The operation cycle is 650 ns. No
= 0: Write the data to the specified indirect register.
= 1: Read the data from the specified indirect register.
Specifies the address of the indirect registers (from 20H to 57H) for the microprocessor access.
This register holds the value which will be read from or written to the indirect registers (from 20H to 57H). If data is to be written to the indirect reg-
BUSY
R/WB
R/W
R/W
D7
R
X
7
0
7
0
7
R/W
R/W
A6
D6
6
6
0
6
X
R/W
R/W
A5
D5
X
5
5
0
5
R/W
R/W
A4
D4
X
4
4
0
4
244
Reserved
R/W
R/W
D3
A3
X
3
3
0
3
R/W
R/W
A2
D2
2
2
0
2
X
T1 / E1 / J1 OCTAL FRAMER
R/W
R/W
A1
D1
X
1
1
0
1
March 5, 2009
R/W
R/W
A0
D0
X
0
0
0
0