IDT82V2108PXG IDT, Integrated Device Technology Inc, IDT82V2108PXG Datasheet - Page 36

• Manufacturer Part Number: IDT82V2108PXG
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG

IDT82V2108
3.9
dently.
3.9.1
ing bits are located in TS16, which is Channel Associated Signaling
(CAS). Their arrangement in TS16 is shown in Figure 6.
naling output, i.e. in Receive Clock Slave External Signaling mode or in
Receive Multiplex mode, the signaling codeword (ABCD) is clocked out
in the lower nibble of the time slot with its corresponding data serializing
on the RSDn/MRSD[1:2] pins (as shown in the Figure 7).
(b5~0, E1-064H and b7~0, E1-065H and b7~0, E1-066H and b7~0, E1-
Functional Description
Figure 6. TS16 Arrangement in Signaling Multi-Frame
F15
The Receive CAS/RBS Buffer of each framer operates indepen-
In the Signaling Multi-Frame synchronization condition, the signal-
When the RSCKn/RSSIGn/MRSSIG[1:2] pins are used as the sig-
When the COSS (b6, E1-064H) is logic 1, all the COSS[30:1]
F0
F1
F2
RECEIVE CAS/RBS BUFFER (RCRB)
MRSSIG[1:2]
MRSD[1:2]
E1 MODE
RSSIGn/
RSDn/
A
A
A
0
Signaling Multi-Frame
alignment pattern
B
B
B
0
to TS15
to TS1
to TS2
1 2 3 4 5 6 78
TS31
C
C
C
0
ABCD
D
D
D
0
TS16
1 2 3 4 5 6 78 1 2 3 4 5 6 78
TS0
X
A
A
A
RMAI
Extra Bits
Y
B
B
B
to TS17
to TS18
to TS31
Figure 7. Signaling Output in E1 Mode
TS1
ABCD
X
C
C
C
X
D
D
D
1 2 3 4 5 6 78 1 2 3 4 5 6 78 1 2 3 4 5 6 78
TS15
26
ABCD
067H) in the Receive CAS/RBS Buffer registers will reflect the change of
the signaling of each time slot respectively (excluding the TS0 and
TS16).
Buffer indirect registers (from 01H to 5FH of RCRB indirect registers)
can be accessed by the microprocessor. The address of the indirect reg-
ister is specified by the A[6:0] (b6~0, E1-066H). Whether the data is
read from or written into the specified indirect register is determined by
the R/WB (b7, E1-066H) and the data is in the D[7:0] (b7~0, E1-067H).
The indirect registers have a read/write cycle. Before the read/write
operation is completed, the BUSY (b7, E1-065H) will be set. New opera-
tions on the indirect registers can only be implemented when the BUSY
(b7, E1-065H) is cleared. The read/write cycle is 490 ns.
ments (from 01H to 1FH & from 21H to 3FH) contain the signaling bits of
each time slot; another segment (from 40H to 5FH) contains the signal-
ing debounce configuration of each time slot.
debounce and signaling freezing.
RCRB-indirect registers - 41~5FH). The DEB (b0, E1-RCRB-indirect
registers - 41~5FH) is activated when the PCCE (b0, E1-064H) is set.
The signaling bits are updated only when 2 consecutive signalings of a
time slot are the same.
out of Signaling Multi-Frame synchronization or in unframed mode.
indirect registers - 01~1FH or b3~0, E1-RCRB-indirect registers -
21~3FH).
COSS[n] (E1-064H and E1-065H and E1-066H and E1-067H) and the
updating of the A, B, C, D code in the corresponding indirect registers
(b3~0, E1-RCRB-indirect registers - 21~3FH). To avoid this 2 ms delay,
users can read the corresponding b3~0 in the E1-RCRB-indirect regis-
ters - (01~1FH) first. If the value of these four bits are different from the
previous A, B, C, D code, then the content of b3~0 in the E1-RCRB-indi-
rect registers - (01~1FH) is the updated A, B, C, D code. If the content of
the four bits is the same as the previous A, B, C, D code, then users
should read the b3~0 in the E1-RCRB-indirect registers - (21~3FH) to
get the updated A, B, C, D code.
rupt on the INT pin if the SIGE (b5, E1-064H) is set.
When the COSS (b6, E1-064H) is logic 0, the Receive CAS/RBS
The indirect registers are divided into three segments: two seg-
A three-Signaling-Multi-Frame capacity buffer is used for signaling
Signaling debounce will be performed by setting the DEB (b0, E1-
Signaling freeze will remain the signaling automatically when it is
The signaling bits are extracted to the A, B, C, D (b3~0, E1-RCRB-
There is a maximum 2 ms delay between the transition of the
Any one of the 30-timeslot’s signaling change will cause an inter-
TS16
TS17
ABCD
1 2 3 4 5 6 78 1 2 3 4 5 6 78
TS31
T1 / E1 / J1 OCTAL FRAMER
ABCD
TS0
March 5, 2009