IDT82V2108PXG IDT, Integrated Device Technology Inc, IDT82V2108PXG Datasheet - Page 85

• Manufacturer Part Number: IDT82V2108PXG
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG

IDT82V2108
3.13.2.3
input the data to all eight framers. Chosen by the MTBS (b6, T1/J1-
015H) in each framer, the data on one of the two multiplexed buses is
byte-interleaved input to up to four framers. When each four framers is
selected, the input sequence of the data on one multiplexed bus is
arranged by setting the channel offset TSOFF[6:0] (b6~0, T1/J1-014H).
The data for a different framer from one multiplexed bus must be shifted
by a different channel offset to avoid data mixing. Then the data on the
multiplexed bus will be input to each of the four selected framers with a
byte-interleaved manner.
is clocked by MTSCCKB. The active edge of MTSCCKB to sample the
data on the MTSCFS, MTSD and MTSSIG pins is determined by the
TSCCKBFALL (b3, T1/J1-004H). The TSCCKBFALL (b3, T1/J1-004H)
of the eight framers should be set to the same value.
System Common Clock B (MTSCCKB) is provided by the system side. It
is used as a common timing clock for all eight framers. The speed of
MTSCCKB can be chosen by the CMS (b5, T1/J1-015H) to be the same
as the data to be transmitted (8.192MHz), or double the data
(16.384MHz). If the speed of MTSCCKB is double the data to be trans-
mitted, there will be two active edges in one bit duration. In this case, the
COFF (b4, T1/J1-015H) determines the active edge to sample the signal
on the MTSD and MTSSIG pins and the active edge to update the pulse
on the MTSFS pin; however, the pulse on MTSCFS is always sampled
Functional Description
MTSSIG
MTSCFS
MTSD
MTSCCKB
LTDn
LTCKn
Line Interface (of any of the Framer1 to Framer4). LTCKn is 1.544M:
In this mode (refer to Figure 45), two multiplexed buses are used to
In the Transmit Multiplexed mode, the data on the system interface
In the Transmit Multiplexed mode, the Multiplexed Transmit Side
D
8
Parity
bit
P
P
Transmit Multiplexed Mode
X
X
X
X
Framer1
X
X
X
CH24-7
X
Figure 61. T1/J1 Transmit Multiplexed Mode - Functional Timing Example 1
X
X
X
X
F-bit
F
X
Parity
P
bit
P
CH24-8
X
X
The TSOFF[6:0] of Framer1 are set to 7'b0000000, the TSOFF[6:0] of Framer2 are set to 7'b0000001,
the TSOFF[6:0] of Framer3 are set to 7'b0000010, the TSOFF[6:0] of Framer4 are set to 7'b0000011,
In this example, Framer1 to Framer4 are supposed to be demultiplexed from one multiplexed bus.
X
X
Framer2
X
X
X
X
The CMS (b5, T1/J1-015H) is logic 0, i.e., the bankplane rate is 8.192Mbit/s.
X
X
X
X
F
the BOFF[2:0] of the four Framers are set to logic 0:
F-bit
F
X
The TSCCKBFALL (b3, T1/J1-004H) is logic 1.
Parity
P
P
bit
X
X
X
X
CH1-1
Framer3
X
X
75
X
X
on its first active edge. If the CMS (b5, T1/J1-015H) or the COFF (b4,
T1/J1-015H) of any of the eight framers is configured as logic 1, all the
others are taken as logic 1. That is, the CMS (b5, T1/J1-015H) and the
COFF (b4, T1/J1-015H) of the eight framers should be configured to the
same value in the Transmit Multiplexed mode.
mon Clock A (TSCCKA) is provided by the system side. It is used as one
of the reference clocks for the transmit jitter attenuator DPLL for all eight
framers (refer to Chapter 3.20 Transmit Clock for details).
System Common Frame Pulse (MTSCFS) is used as a common framing
signal to align data streams on the two multiplexed buses. MTSCFS is
asserted on the F-bit of the selected first framer. The valid polarity of
MTSCFS is configured by the FPINV (b5, T1/J1-005H). The FPINV (b5,
T1/J1-005H) of the eight framers should be the same value.
8.192Mb/s.
to be inserted. The signaling bits are channel aligned with the data input
from MTSD. The signaling on the MTSSIG pin may be configured by the
ABXXEN (b4, T1/J1-005H) to be valid only in the upper two-bit positions
of the lower nibble of each channel (i.e. XXXXABXX) in T1 ESF mode.
each channel is the first bit to be transmitted.
X
X
In the Transmit Multiplexed mode, the Transmit Side System Com-
In the Transmit Multiplexed mode, the Multiplexed Transmit Side
In the Transmit Multiplexed mode, the bit rate on the MTSD pin is
In the Transmit Multiplexed mode, MTSSIG input the signaling bits
Figure 61 & Figure 62 show the functional timing examples. Bit 1 of
X
X
F-bit
F
X
Parity
P
bit
P
CH1-2
X
X
X
X
X
Framer4
X
X
X
X
X
CH1-3
X
X
F-bit
F
X
X
1
T1 / E1 / J1 OCTAL FRAMER
X
2
3
X
CH1-4
Framer1_CH1
X
4
A
5
6
B
March 5, 2009
C
7
CH1-5
D
8