IDT82V2108PXG IDT, Integrated Device Technology Inc, IDT82V2108PXG Datasheet - Page 156

• Manufacturer Part Number: IDT82V2108PXG
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG

IDT82V2108
E1 Receive Backplane Time Slot Offset (013H, 093H, 113H, 193H, 213H, 293H, 313H, 393H)
pins. If RSCFS does not exist, the time slot offset is between RSFSn and the start of the Basic Frame output on RSDn & RSSIGn. In Receive Multi-
plexed mode, each framer contributes every fourth time slot on MRSD[1:2] and MRSSIG[1:2].
E1 Receive Backplane Bit Offset (014H, 094H, 114H, 194H, 214H, 294H, 314H, 394H)
RSD_RSCFS_EDGE:
is used to update the signal on the MRSD, MRSSIG and MRSFS pins.
is used to update the signal on the MRSD, MRSSIG and MRSFS pins.
SIG and RSFSn/MRSFS pins are updated on the first active edge of RSCCK/MRSCCK.
BOFF_EN:
BOFF[2:0]:
the Basic Frame output on the RSDn & RSSIGn pins. If RSCFS does not exist, the time slot offset is between RSFSn and the start of the Basic Frame
output on RSDn & RSSIGn. It is also available in Receive Multiplexed mode.
the Functional Description for details.
Programming Information
Bit Name
Bit Name
Default
Bit No.
Default
Bit No.
Type
These bits determine the time slot offset between the signal on the RSCFS pin and the start of the Basic Frame output on the RSDn & RSSIGn
They define a binary number. The offset can be set from 0 to 127 time slots.
Valid when the CMS (b2, E1-010H) is logic 1 and the DE (b4, E1-010H) is not equal to the FE (b3, E1-010H).
= 0: The second active edge of RSCCK is used to update the signal on the RSDn, RSSIGn and RSFSn pins, or the first active edge of MRSCCK
= 1: The first active edge of RSCCK is used to update the signal on the RSDn, RSSIGn and RSFSn pins, or the second active edge of MRSCCK
(The signal on the RSCFS/MRSCFS pin is always sampled on the first active edge.)
In Receive Multiplexed mode, the RSD_RSCFS_EDGE in all eight framers should be set to the same value.
When the CMS (b2, E1-010H) is logic 1 and the DE (b4, E1-010H) is equal to FE (b3, E1-010H), the signals on the RSDn/MRSD, RSSIGn/MRS-
Valid when the CMS (b2, E1-010H) is logic 0.
= 0: Disable the bit offset.
= 1: Enable the bit offset.
Valid when the CMS (b2, E1-010H) is logic 0 and the BOFF_EN is logic 1.
These bits define a binary number. The content in the BOFF[2:0] determines the bit offset between the signal on the RSCFS pin and the start of
Programming of the Bit Offsets is consistent with the convention established by the Concentration Highway Interface (CHI) specification. Refer to
Type
Reserved
7
7
Reserved
TSOFF[6]
R/W
6
0
6
RSD_RSCFS_EDGE
TSOFF[5]
R/W
5
0
R/W
5
0
TSOFF[4]
R/W
4
0
Reserved
146
4
TSOFF[3]
R/W
BOFF_EN
3
0
R/W
3
0
TSOFF[2]
R/W
BOFF[2]
2
0
R/W
2
0
T1 / E1 / J1 OCTAL FRAMER
TSOFF[1]
BOFF[1]
R/W
R/W
1
0
1
0
March 5, 2009
TSOFF[0]
BOFF[0]
R/W
R/W
0
0
0
0