IDT82V2108PXG IDT, Integrated Device Technology Inc, IDT82V2108PXG Datasheet - Page 169

• Manufacturer Part Number: IDT82V2108PXG
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG

IDT82V2108
E1 THDLC Transmit Data Link 3 Control (TXCISEL = 1) (02CH, 0ACH, 12CH, 1ACH, 22CH, 2ACH, 32CH, 3ACH)
DL3_EVEN:
DL3_ODD:
DL3_TS[4:0]:
both logic 0.
E1 THDLC Data Link 3 Bit Select (TXCISEL = 1) (02DH, 0ADH, 12DH, 1ADH, 22DH, 2ADH, 32DH, 3ADH)
DL3_BITn:
Programming Information
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Type
Type
When the TXCISEL (b3, E1-00AH) is ‘1’, this register is used for the Transmit HDLC #3.
= 0: The data is not inserted to the even frames.
= 1: The data is inserted to the even frames.
The even frames are FAS frames.
= 0: The data is not inserted to the odd frames.
= 1: The data is inserted to the odd frames.
The odd frames are NFAS frames.
The data is inserted into the time slot defined by the binary number in these bits. They are invalid when the DL3_EVEN and the DL3_ODD are
When the TXCISEL (b3, E1-00AH) is ‘1’, this register is used for the Transmit HDLC #3.
= 0: The data is not inserted to the corresponding bit.
= 1: The data is inserted to the corresponding bit of the assigned time slot.
These bits are invalid when the DL3_EVEN and the DL3_ODD are both logic 0.
The DL3_BIT[7] corresponds to the first bit (MSB) of the selected time slot.
DL3_EVEN
DL3_BIT[7]
R/W
R/W
7
0
7
0
DL3_BIT[6]
DL3_ODD
R/W
R/W
6
0
6
0
DL3_BIT[5]
Reserved
R/W
5
5
0
DL3_BIT[4]
DL3_TS[4]
R/W
R/W
4
0
4
0
159
DL3_BIT[3]
DL3_TS[3]
R/W
R/W
3
0
3
0
DL3_BIT[2]
DL3_TS[2]
R/W
R/W
2
0
2
0
T1 / E1 / J1 OCTAL FRAMER
DL3_BIT[1]
DL3_TS[1]
R/W
R/W
1
0
1
0
March 5, 2009
DL3_BIT[0]
DL3_TS[0]
R/W
R/W
0
0
0
0