IDT82V2108PXG IDT, Integrated Device Technology Inc, IDT82V2108PXG Datasheet - Page 231

• Manufacturer Part Number: IDT82V2108PXG
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG

IDT82V2108
T1 / J1 RJAT Output Clock Divisor (N2) Control (012H, 092H, 112H, 192H, 212H, 292H, 312H, 392H)
output smoothed clock and the frequency applied to the phase discriminator input.
T1 / J1 RJAT Configuration (013H, 093H, 113H, 193H, 213H, 293H, 313H, 393H)
CENT:
UNDE:
OVRE:
LIMIT:
the read pointer is 1 UI away from the FIFO being empty or full. This limitation of jitter attenuation ensures that no data is lost during high phase shift
conditions.
Programming Information
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Type
Type
These bits define a binary number. The (N2[7:0] + 1) is the divisor of the output smoothed clock, which is the ratio between the frequency of the
Writing to this register will reset the DPLL in the RJAT.
The CENT allows the RJAT FIFO to self-center its read pointer, maintaining the pointer at least 4 UI away from the FIFO being empty or full.
= 0: Disable the self-center. Data passes through uncorrupted when the FIFO is empty or full.
= 1: Enable the FIFO to self-center its read pointer when the FIFO is 4 UI away from being empty or full.
A positive transition in this bit will execute a self-center action immediately.
This bit decides whether to generate an interrupt when the RJAT FIFO is under-run.
= 0: No interrupt is generated when the RJAT FIFO is under-run.
= 1: An interrupt on the INT pin is generated when the RJAT FIFO is under-run.
This bit decides whether to generate an interrupt when the RJAT FIFO is overwritten.
= 0: No interrupt is generated when the RJAT FIFO is overwritten.
= 1: An interrupt on the INT pin is generated when the RJAT FIFO is overwritten.
= 0: Disable the limitation of the jitter attenuation.
= 1: Enable the DPLL to limit the jitter attenuation by enabling the FIFO to increase or decrease the frequency of the output smoothed clock when
N2[7]
R/W
7
0
7
Reserved
N2[6]
R/W
6
0
6
N2[5]
R/W
5
1
5
CENT
N2[4]
R/W
R/W
4
0
4
0
221
UNDE
N2[3]
R/W
R/W
3
1
3
0
OVRE
N2[2]
R/W
R/W
2
1
2
0
T1 / E1 / J1 OCTAL FRAMER
Reserved
N2[1]
R/W
1
1
1
March 5, 2009
LIMIT
N2[0]
R/W
R/W
0
1
0
1