IDT82V2108PXG IDT, Integrated Device Technology Inc, IDT82V2108PXG Datasheet - Page 238

• Manufacturer Part Number: IDT82V2108PXG
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG

IDT82V2108
T1 / J1 Clock Monitor (027H, 0A7H, 127H, 1A7H, 227H, 2A7H, 327H, 3A7H)
in this register is set to ‘1’, and this bit remains to be ‘1’ until this register is read. After a read operation on this register, all the bits in this register will
be cleared to ‘0’. A lack of transitions of the monitored clock will be indicated by ‘0’ in the corresponding bit, which means that the clock fails. This reg-
ister should be read periodically to detect clock failures.
XCK:
TSCCKB:
TSCCKA:
RSCCK:
LRCK:
Programming Information
Bit Name
Default
Bit No.
Type
= 0: The received data stream is out-of-frame.
= 1: The received data stream is in-frame.
Read operation will not change the status of this bit.
This register provides monitoring on the IDT82V2108 clocks. When a monitored clock signal makes a low to high transition, the corresponding bit
= 0: After the bit is read.
= 1: A low to high transition occurs on XCK.
= 0: After the bit is read.
= 1: A low to high transition occurs on TSCCKB.
= 0: After the bit is read.
= 1: A low to high transition occurs on TSCCKA.
= 0: After the bit is read.
= 1: A low to high transition occurs on RSCCK.
= 0: After the bit is read.
= 1: A low to high transition occurs on LRCK.
7
Reserved
6
5
XCK
R
X
4
228
TSCCKB
R
X
3
TSCCKA
R
2
X
T1 / E1 / J1 OCTAL FRAMER
RSCCK
R
X
1
March 5, 2009
LRCK
R
X
0