IDT82V2108PXG IDT, Integrated Device Technology Inc, IDT82V2108PXG Datasheet - Page 30

• Manufacturer Part Number: IDT82V2108PXG
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG

IDT82V2108
3.3
events in the received data stream within defined intervals. The Perfor-
mance Monitor of each framer operates independently.
3.3.1
The method of counting the errors is defined by the WORDERR (b5, E1-
000H) and CNTNFAS (b4, E1-000H) as shown in Table 6. The number
of the Basic Frame alignment pattern errors counted during the interval
is reflected in the FER[6:0] (b6~0, E1-069H).
Table 6: Basic Frame Alignment Pattern Error Counter
detected in the E1 and E2 bits. The number of the FEBE counted during
the interval is stored in the FEBE[9:0] (b1~0, E1-06BH & b7~0, E1-
06AH).
lated CRC remainders are not equal to the received CRC. The number
of the CRC errors counted during the interval is indicated in the
CRCE[9:0] (b1~0, E1-06DH & b7~0, E1-06CH).
vated when the framer is out of Basic Framer synchronization. The latter
two kinds of PMON Error Count registers are also deactivated when it is
out of CRC Multi-Frame synchronization.
a group. The intervals are typically 1 second when the AUTOUPDATE
(b0, E1-000H) of the current framer is set. They can also be updated by
writing to any of these PMON Error Count registers. The PMON Error
Count registers in eight framers can also be updated together by writing
to the Revision / Chip ID / Global PMON Update register (E1-009H).
Once the PMON Error Count registers are updated, the XFER (b1, E1-
068H) will be set to logic 1 and an interrupt can be asserted on the INT
pin if the INTE (b2, E1-068H) is logic 1.
its PMON Error Count register without the previous one being read, the
PMON Error Count register is over-written. Any over-writing of the three
kinds of PMON Error Count registers will be indicated in the OVR (b0,
E1-068H).
Functional Description
(b5, E1-000H)
WORDERR
The Performance Monitor is used to count various performance
The PMON block counts the Basic Frame alignment pattern errors.
The PMON block counts the Far End Block Error (FEBE) which is
The block also counts the CRC errors which mean the local calcu-
The above three kinds of PMON Error Count registers are deacti-
These PMON Error Count registers in a framer can be updated as
If the performance number counted in the next interval is latched in
0
0
1
1
PERFORMANCE MONITOR (PMON)
E1 MODE
CNTNFAS (b4,
E1-000H)
0
1
0
1
One bit error in FAS
One bit error in FAS or a logic 0 in bit 2 of TS0
of NFAS
One or more than one bit error in a FAS
Any bit error in a FAS and the 2nd bit of TS0 of
the following NFAS
One Error is Counted
20
3.3.2
events:
number of the errors counted during the interval is reflected in the
FER[8:0] (b0, T1/J1-04DH & b7~0, T1/J1-04CH) (In SF format, the
usage of the BEE[11:0] (b3~0, T1/J1-04BH & b7~0, T1/J1-04AH) is the
same as that of the FER[8:0]);
counted during the interval is reflected in the OOF[4:0] (b4~0, T1/J1-
04EH);
the interval is counted and is reflected in the COFA[2:0] (b2~0, T1/J1-
04FH).
events:
lated CRC-6 remainders are not equal to the received CRC-6. The num-
ber of the errors counted during the interval is indicated in the BEE[11:0]
(b3~0, T1/J1-04BH & b7~0, T1/J1-04AH);
above.)
a group. The intervals are typically 1 second when the AUTOUPDATE
(b0, T1/J1-000H) of the framer is set. They can also be updated by writ-
ing to any of these PMON Error Count registers. The PMON Error Count
registers of eight framers can also be updated together by writing to the
Revision / Chip ID / Global PMON Update register (T1/J1-00CH). Once
the PMON Error Count registers are updated, the XFER (b1, T1/J1-
049H) will be logic 1 and an interrupt can be asserted on the INT pin if
the INTE (b2, T1/J1-049H) is logic 1.
its PMON register without the previous one being read, the PMON Error
Count register is over-written. Any over-writing of the four kinds of
PMON Error Count registers will be indicated in the OVR (b0, T1/J1-
049H).
In the SF format, the Performance Monitor counts three kinds of
1. Every one-bit error in a frame alignment pattern is counted. The
2. The out of SF synchronization event is counted. The number
3. The number of changes of the frame alignment position during
In the ESF format, the Performance Monitor counts four kinds of
1. The block counts the CRC-6 errors which mean the local calcu-
2 ~ 4. (The same events as 1 ~ 3 in the SF format, described
These PMON Error Count registers in a framer can be updated as
If the performance number counted in the next interval is latched in
T1/J1 MODE
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009