IDT82V2108PXG IDT, Integrated Device Technology Inc, IDT82V2108PXG Datasheet - Page 51

• Manufacturer Part Number: IDT82V2108PXG
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG

IDT82V2108
3.11.1.4
tional E1 (with F-bit) mode, if the RPTYE (b6, E1-012H) is logic 1, parity
check will be conducted over the bits in the previous Basic Frame and
the result is inserted into the first bit (MSB) of TS0 on the RSDn/MRSD
pin. The even parity or odd parity is chosen by the RPTYP (b7, E1-
012H) and whether the first bit of TS0 is calculated or not is determined
by the PTY_EXTD (b3, E1-012H). Alternatively this first bit of TS0 can
be forced to be logic 0 or 1 by setting the value in the FIXPOL (b4, E1-
013H). The TSOFF[6:0] (b6~0, E1-013H) give a binary representation.
ured in the BOFF[2:0] (b2~0, E1-014H). The bit offset follows the Con-
centration Highway Interface (CHI) specification (refer to Table 17 &
Table 18). When the bit offset is between RSCFS/MRSCFS and the start
of the corresponding frame on RSDn/MRSD, the CET (clock edge trans-
mit) is counted from the active edge of RSCFS/MRSCFS (refer to the
example in Figure 22). The pulse on RSFSn/MRSFS and the signal on
RSSIGn/MRSSIG (if it exists) are aligned to RSDn/MRSD. When the bit
Table 18: Receive System Interface Bit Offset (FPMODE [b5, E1-011H] = 1)
Functional Description
Table 16: Offset in Different Operation Modes
Table 17: Receive System Interface Bit Offset (FPMODE [b5, E1-011H] = 0)
FE (b3, E1-010H) DE (b4, E1-010H)
Receive Clock Master mode
Receive Clock Slave mode
Receive Multiplexed mode
FE (b3, E1-010H)
In all the above modes except for the Receive Clock Slave Frac-
The time slot offset is configured in the TSOFF[6:0] (b6~0, E1-
Enabled by the BOFF_EN (b3, E1-014H), the bit offset is config-
Operation Mode
0
0
1
1
0
0
1
1
Parity Check & Polarity Fix
DE (b4, E1-010H)
0
1
0
1
1 (in any of the eight framers) The offset is between MRSCFS and the start of the corresponding frame on MRSD and MRSSIG.
0
1
0
1
FPMODE (b5, E1-011H)
0 (must be zero)
000
2
1
1
2
1
0
0
000
4
3
3
4
001
4
3
3
4
001
6
5
5
6
The offset is between RSCFS and the start of the corresponding frame on RSDn (and RSSIGn).
The offset is between RSFSn and the start of the corresponding frame on RSDn (and RSSIGn).
The offset is between RSFSn and the start of the corresponding frame on RSDn.
The offset is between MRSFS and the start of the corresponding frame on MRSD and MRSSIG.
010
6
5
5
6
010
8
7
7
8
41
012H) when the FIXF (b5, E1-012H) is set. The priority of the FIXF (b5,
E1-012H) is lower than the RPTYE (b6, E1-012H).
3.11.1.5
configured. If the offset is configured, the offset between different opera-
tion modes is summarized in Table 16. Bit offset is disabled when the
CMS (b2, E1-010H) is logic 1.
offset is between RSFSn/MRSFS and the start of the corresponding
frame on RSDn/MRSD, the CET is counted from the active edge of
RSFSn/MRSFS (refer to the example in Figure 23). The signal on
RSSIGn/MRSSIG (if it exists) is aligned to RSDn/MRSD.
(b2, b0, E1-011H) are both set to logical 1. In this case, there is bit offset
between the output on RSFSn and RSDn. Refer to Table 19 for the
details.
011
BOFF[2:0] (b2~0, E1-014H)
8
7
7
8
In the above five modes, time slot offset and/or bit offset can be
Note that it is a special case when the BRXSMFP and the ALTIFP
011
BOFF[2:0] (b2~0, E1-014H)
10
10
9
9
Offset
100
10
10
9
9
100
12
11
11
12
Offset
101
12
11
11
12
101
14
13
13
14
T1 / E1 / J1 OCTAL FRAMER
110
14
13
13
14
110
16
15
15
16
111
111
18
17
17
18
16
15
15
16
March 5, 2009
CET
CET