IDT82V2108PXG IDT, Integrated Device Technology Inc, IDT82V2108PXG Datasheet - Page 18

• Manufacturer Part Number: IDT82V2108PXG
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG

IDT82V2108
Pin Description
TSCCKB / MTSCCKB
TSFS[1] / TSSIG[1] /
TSFS[2] / TSSIG[2] /
TSFS[3] / TSSIG[3]
TSFS[4] / TSSIG[4]
TSFS[5] / TSSIG[5]
TSFS[6] / TSSIG[6]
TSFS[7] / TSSIG[7]
TSFS[8] / TSSIG[8]
TSCFS / MTSCFS
MTSSIG[1]
MTSSIG[2]
TSCCKA
LTD[1]
LTD[2]
LTD[3]
LTD[4]
LTD[5]
LTD[6]
LTD[7]
LTD[8]
Name
Output /
Output
Type
Input
Input
Input
Input
PQFP PBGA
106
104
102
100
123
122
121
114
112
110
98
11
13
15
22
24
26
28
9
Pin No.
C10
A10
B10
G3
A7
B8
C7
D8
C9
A4
B4
C5
D2
E3
F4
E1
H1
J2
J3
TSFS[1:8]: Transmit Side System Frame Pulse for Framer 1 ~ 8
In Transmit Clock Master mode, TSFSn indicates the beginning of each Basic Frame in E1 mode, or indicates the
F-bit of SF/ESF in T1/J1 mode. TSFSn is updated on the active edge of the corresponding LTCKn.
In Transmit Clock Slave TSFS Enabled mode, TSFSn indicates the beginning of each Basic Frame in E1 mode, or
indicates the F-bit of SF/ESF in T1/J1 mode. TSFSn is updated on the active edge of TSCCKB.
TSSIG[1:8]: Transmit Side System Signaling for Framer 1 ~ 8
In Transmit Clock Slave External Signaling mode, these are the TSSIG inputs. The signaling is located in the lower
nibble (b5 ~ b8) and sampled on the active edge of TSCCKB. In E1 mode, the signaling repeats during the entire
Signaling Multi-Frame for the same time slot. In T1/J1 mode, the signaling repeats during the entire SF/ESF for the
same channel.
MTSSIG[1:2]: Multiplexed Transmit Side System Signaling
When the multiplexed bus structure is configured, the signaling on the bus is organized in a byte-interleaved
scheme for the selected framers. MTSSIG[1:2] are sampled on the active edge of MTSCCKB.
TSCCKA: Transmit Side System Common Clock A
TSCCKA is one of the reference clocks for the transmit jitter attenuator DPLL. TSCCKA can be configured to input
the clock as:
1. 16.384MHz clock;
2. Line rate: 2.048MHz (for E1) or 1.544MHz (for T1);
3. Nx8KHz (N is from 1 to 256) so long as TSCCKA is a jitter-free clock.
The IDT82V2108 can be configured to ignore TSCCKA and utilize LRCK and TSCCKB instead. TSCCKA is
replaced by LRCK if line loopback is enabled.
TSCCKB: Transmit Side System Common Clock B
In E1 mode, TSCCKB is a 2.048 or 4.096 MHz clock. In T1/J1 mode, TSCCKB is a 1.544 or 2.048 or 4.096 MHz
clock.
In Transmit Clock Slave TSFS mode, TSDn and TSCFS are sampled and TSFSn is updated on the active edge of
TSCCKB. In Transmit Clock Slave External Signaling mode, TSDn, TSSIGn and TSCFS are sampled on the active
edge of TSCCKB.
MTSCCKB: Multiplexed Transmit Side System Common Clock B
When the multiplexed bus structure is configured, MTSCCKB is an 8.192 or 16.384 MHz reference clock for the
transmit system multiplexed bus. MTSCFS, MTSD[1:2] and MTSSIG[1:2] are sampled on the active edge of MTSC-
CKB.
TSCFS: Transmit Side System Common Frame Pulse
In Transmit Clock Slave mode, TSCFS is used to frame align all the framers to the system backplane. In E1 mode,
the pulse can be configured to indicate the first bit of a Basic Frame, CRC Multi-Frame / Signaling Multi-Frame. In
T1/J1 mode, the pulse can be configured to indicate the first bit of SF/ESF. The width of the pulse must be at least 1
TSCCKB cycle wide. TSCFS is sampled on the active edge of TSCCKB.
MTSCFS: Multiplexed Transmit Side System Common Frame Pulse
When the multiplexed bus structure is configured, MTSCFS is used to frame align the multiplexed frames to the
system backplane. MTSCFS is sampled on the active edge of MTSCCKB.
LTD[1:8]: Line Transmit Data for Framer 1 ~ 8
These pins output the data stream to line interface units or a higher multiplex interface.
The data on LTDn is updated on the active edge of the corresponding LTCKn.
8
Description
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009