IDT82V2108PXG IDT, Integrated Device Technology Inc, IDT82V2108PXG Datasheet - Page 209

• Manufacturer Part Number: IDT82V2108PXG
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG

IDT82V2108
E1 RCRB Time Slot / Channel Signaling Data Registers (COSS = 0) (RCRB Indirect Registers 01H ~ 1FH / 21H ~ 3FH)
A, B, C, D:
A, B, C, D code in the corresponding indirect registers 21H ~ 3FH. To avoid this 2 ms delay, users can read the corresponding b3~0 in the indirect reg-
isters 01H ~ 1FH first. If the value of these four bits is different from the previous A, B, C, D code, then the content of b3~0 in the 01H ~ 1FH is the
updated A, B, C, D code. If the content of the four bits is the same as the previous A, B, C, D code, then users should read the b3~0 in the 21H ~ 3FH
to get the updated A, B, C, D code.
E1 RCRB Per-Timeslot Configuration Registers (COSS = 0) (RCRB Indirect Registers 40H ~ 5FH)
DEB:
of a time slot are the same.
Programming Information
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Type
Type
They contain the signaling of the corresponding time slot. The value for TS0 and TS16 is not valid.
There is a maximum 2 ms delay between the transition of the COSS[n] bit (E1-064H & E1-065H & E1-066H & E1-067H) and the updating of the
= 0: Disable signaling debounce.
= 1: Enable signaling debounce (valid only if the PCCE is logic 1). That is, the signaling is acknowledged only when 2 consecutive signaling bits
7
7
01H ~ 0FH / 21H ~ 2FH
11H ~ 1FH / 31H ~ 3FH
40H ~ 5FH
10H, 30H
6
6
20H
Reserved
5
5
RCRB Indirect Registers Map
Reserved
4
4
199
Signaling Data Register for TS17 ~31
Signaling Data Register for TS1 ~ 15
TS0 ~ 31 Configuration Data
A
R
X
3
3
-
-
R
2
B
X
2
T1 / E1 / J1 OCTAL FRAMER
C
R
X
1
1
March 5, 2009
DEB
R/W
D
R
X
0
X
0