IDT82V2108PXG IDT, Integrated Device Technology Inc, IDT82V2108PXG Datasheet - Page 73

• Manufacturer Part Number: IDT82V2108PXG
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG

IDT82V2108
3.13.1.3
input the data to all eight framers. Chosen by the MTBS (b4, E1-003H)
in each framer, the data on one of the two multiplexed buses is byte-
interleaved input to up to four framers. When a group of four framers is
selected, the input sequence of the data on the multiplexed bus is
is clocked by MTSCCKB. The active edge of MTSCCKB to sample the
data on MTSCFS, MTSD and MTSSIG is determined by the following
bits in the registers (refer to Table 30).
Table 30: Active Edge Selection of MTSCCKB (in E1 Transmit
Multiplexed Mode)
System Common Clock B (MTSCCKB) is provided by the system side. It
is used as a common timing clock for all eight framers. The speed of
MTSCCKB can be chosen by the CMS (b2, E1-018H) to be the same as
the data to be transmitted (8.192MHz), or double the data (16.384MHz).
If the speed of MTSCCKB is double the data to be transmitted, there will
be two active edges in one bit duration. In this case, the COFF (b4, E1-
01CH) determines the active edge to sample the signals on the MTSD
and MTSSIG pins and the active edge to update the pulse on the
Functional Description
Note:
If the FE is not equal to the DE, the active edge decided by the FE is one clock edge
before the active edge decided by the DE.
The FE and the DE of the eight framers should be set to the same value respectively.
In this mode (refer to Figure 45), two multiplexed buses are used to
In the Transmit Multiplexed mode, the data on the system interface
In the Transmit Multiplexed mode, the Multiplexed Transmit Side
MTSCFS
MTSSIG
MTSD
Transmit Multiplexed Mode
TSCCKA
MTSCCKB
MTSCFS *
MTSD[1:2] *
MTSSIG[1:2] *
Note: * MTSCFS, MTSD, MTSSIG are timed to MTSCCKB
the Bit Determining the Active Edge of MTSCCKB
Transmit
Interface
DE (b4, E1-018H)
FE (b3, E1-018H)
System
Figure 45. Transmit Multiplexed Mode
The Other Four of the Framer #1~#8
Any Four of the Framer #1~#8
Generator
Generator
Frame
Frame
Generator
Generator
Frame
Frame
Generator
Generator
Frame
Frame
63
arranged by setting the time slot offset TSOFF[6:0] (b6~0, E1-01BH).
The data to different framers from one multiplexed bus must be shifted
to a different time slot offset to avoid data mixing. Then the data on the
multiplexed bus will be input to each of the four selected framers with a
byte-interleaved manner.
MTSFS pin; however, the pulse on MTSCFS is always sampled on its
first active edge. However, if the CMS (b2, E1-018H) or the COFF (b4,
E1-01CH) of any of the eight framers is configured as logic 1, all the oth-
ers are taken as logic 1. That is, the CMS (b2, E1-018H) and the COFF
(b4, E1-01CH) of the eight framers should be configured to the same
value in the Transmit Multiplexed mode.
mon Clock A (TSCCKA) is provided by the system side. It is used as one
of the reference clocks for the transmit jitter attenuator DPLL for all eight
framers (refer to Chapter 3.20 Transmit Clock for details).
System Common Frame Pulse (MTSCFS) is used as a common framing
signal to align data streams on the two multiplexed buses. MTSCFS is
asserted on each Basic Frame of the selected first framer. The valid
polarity of MTSCFS is configured by the FPINV (b3, E1-019H). The
FPINV (b3, E1-019H) of the eight framers should be set to the same
value.
8.192Mb/s.
to be inserted. The signaling bits are time slot aligned with the data input
from MTSD. The signaling bits may replace the data on TS16 when the
CCS is disabled and the SIGSRC (b4, E1-TPLC-indirect registers -
61~7FH) in the TPLC block is logic 0.
each time slot is the first bit to be transmitted.
In the Transmit Multiplexed mode, the Transmit Side System Com-
In the Transmit Multiplexed mode, the Multiplexed Transmit Side
In the Transmit Multiplexed mode, the bit rate on the MTSD pin is
In the Transmit Multiplexed mode, MTSSIG inputs the signaling bits
Figure 46 & Figure 47 show the functional timing examples. Bit 1 of
DPLL
DPLL
DPLL
FIFO
DPLL
DPLL
DPLL
DPLL
FIFO
FIFO
DPLL
DPLL
FIFO
FIFO
T1 / E1 / J1 OCTAL FRAMER
LRCK[1:8]
LTCK[1:8]
LTD[1:8]
March 5, 2009