IDT82V2108PXG IDT, Integrated Device Technology Inc, IDT82V2108PXG Datasheet - Page 204

• Manufacturer Part Number: IDT82V2108PXG
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG

IDT82V2108
E1 TPLC Per-TS Control Registers (TPLC Indirect Registers 20H ~ 3FH)
SUBS, DS1, DS0:
TEST:
the test pattern from PRGD to replace the data in the corresponding time slot for test (when the RXPATGEN [b2, E1-00CH] is logic 0).
Similarly, all time slots set to be replaced with PRGD test pattern data are concatenated replaced by the PRBS.
LOOP:
data to be transmitted. When Receive Clock Slave modes are enabled, the Elastic Store is unavailable to facilitate the payload loopbacks, and loop-
back functionality is provided only when the transmit path is also in Transmit Clock Slave mode, and the received clock and the clock to be transmitted
and Common Frame Pulse are identical (RSCCK = TSCCKB, RSCFS = TSCFS).
PRGD; Replace the data with the value in the IDLE[7:0]; Invert the even bits or/and odd bits.
Programming Information
Bit Name
Default
Bit No.
Type
The SUBS, DS[1:0] bits select one of the operations to the corresponding time slot:
= 0: Disable the data in the corresponding time slot to be tested by PRGD.
= 1: Enable the data in the corresponding time slot to be extracted to PRGD for test (when the RXPATGEN [b2, E1-00CH] is logic 1), or enable
All the time slots that are extracted to the PRGD are concatenated and treated as a continuous stream in which pseudo random is searched for.
= 0: Disable the payload loopback.
= 1: Enable the payload loopback. When Receive Clock Master modes are enabled, the Elastic Store is used to align the receive line data to the
The priority of the TPLC operation on the TSDn pin from high to low is:
Extract data to PRGD for test; Payload loopback; Replace the data with the milliwatt pattern; Replace the data with the pattern generated in the
SUBS
0
0
0
0
1
1
1
SUBS
R/W
X
7
DS[1]
0
1
0
1
0
1
-
Reserved
6
20H ~ 3FH
40H ~ 5FH
61H ~ 7FH
DS[0]
0
0
1
1
0
1
1
DS1
R/W
X
5
TPLC Indirect Registers Map
Replace the time slot with the A-law digital milliwatt pattern (per G.711)
Replace the time slot with the µ-law digital milliwatt pattern (per G.711)
Invert the even bits (2, 4, 6, 8) of the time slot (bit 8 is the MSB)
DS0
R/W
Invert the odd bits (1, 3, 5, 7) of the time slot (bit 1 is the LSB)
X
4
194
Signaling /PCM Control Byte for TS1 ~ TS31
Replace the time slot with the IDLE code
Per-TS Control Byte for TS0 ~ TS31
Invert all the bits of the time slot
IDLE Code Byte for TS0 ~ TS31
No change to the time slot
TEST
R/W
X
3
OPERATION
LOOP
R/W
2
X
T1 / E1 / J1 OCTAL FRAMER
1
Reserved
March 5, 2009
0