IDT82V2108PXG IDT, Integrated Device Technology Inc, IDT82V2108PXG Datasheet - Page 210

• Manufacturer Part Number: IDT82V2108PXG
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG

IDT82V2108
E1 PMON Interrupt Enable / Status (068H, 0E8H, 168H, 1E8H, 268H, 2E8H, 368H, 3E8H)
INTE:
XFER:
OVR:
Registers 069H-06DH, 0E9H-0EDH, 16H-16DH, 1E9H-1EDH, 269H-26DH,2E9H-2EDH,369H-36DH, 3E9H-3EDH:
second when the AUTOUPDATE (b0, E1-000H) is set. The PMON Error Count registers for eight framers are updated by writing to the Chip ID/Global
PMON Update register (E1-009H).
E1 PMON Framing Bit Error Count (069H, 0E9H, 169H, 1E9H, 269H, 2E9H, 369H, 3E9H)
update on the defined intervals. The basic frame alignment signal errors are defined in the WORDERR (b5, E1-000H) and the CNTNFAS (b4, E1-
000H).
Programming Information
Bit Name
Bit Name
Default
Bit No.
Default
Bit No.
Type
= 0: Disable the interrupt on the INT pin when the counter data has been transferred into the Error Count registers.
= 1: Enable the interrupt on the INT pin when the counter data has been transferred into the Error Count registers.
= 0: Indicate that the counter data has not been transferred to the Error Count registers.
= 1: Indicate that the counter data has been transferred to the Error Count registers.
This bit is clear to ‘0’ after the bit is read.
= 0: Indicate that no overwritten on the Error Count registers has occurred.
= 1: Indicate that one of the Error Count registers is overwritten.
This bit is clear to ‘0’ after the bit is read.
The PMON Error Count registers for a single framer are updated as a group by writing to any of the PMON count registers or updated every 1
When the chip is reset, the contents of the PMON Error Count registers are unknown until the first latching of performance data is performed.
Type
These bits are valid when it is in the Basic Frame Synchronization. They represent the number of the basic frame alignment signal errors and
Reserved
7
7
FER[6]
6
R
X
6
Reserved
FER[5]
5
R
X
5
FER[4]
R
X
4
4
200
FER[3]
R
X
3
3
FER[2]
INTE
R/W
R
X
2
0
2
T1 / E1 / J1 OCTAL FRAMER
FER[1]
XFER
R
X
R
1
1
0
March 5, 2009
FER[0]
OVR
R
X
R
0
0
0