IDT82V2108PXG IDT, Integrated Device Technology Inc, IDT82V2108PXG Datasheet - Page 224

• Manufacturer Part Number: IDT82V2108PXG
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG

IDT82V2108
T1 / J1 Transmit Framing and Bypass Options (006H, 086H, 106H, 186H, 206H, 286H, 306H, 386H)
FRESH:
SIGAEN:
FDIS:
FBITBYP:
CRCBYP:
FDLBYP:
Programming Information
Bit Name
Default
Bit No.
Type
= 0: Normal operation.
= 1: Initiate the FIFO in the Frame Generator block.
After initialization of the backplane interface, the user should write ‘1’ into this bit and then clear it.
= 0: Track the signaling input from the TSSIGn/MTSSIG pin as the signaling bit.
= 1: Take a snapshot of the 1st frame input from the TSSIGn/MTSSIG pin and lock it for the signaling bit of the whole SF/ESF.
This bit is valid when the UF (b6, T1/J1-046H) is logic 0.
= 0: The Frame Generator is enabled to generate and insert the framing bits into the transmit data.
= 1: The Frame Generator is bypassed. Data on the TSDn/MTSD pin is transmitted transparently.
This bit is valid when the UF (b6, T1/J1-046H) and the FDIS (b3, T1/J1-006H) are logic 0.
= 0: The frame synchronization bits in the output data stream are generated by the Frame Generator.
= 1: The frame synchronization bits in the input data stream on the TSDn/MTSD pin will be output transparently.
This bit is valid when the UF (b6, T1/J1-046H) and the FDIS (b3, T1/J1-006H) are logic 0.
= 0: The framing bit corresponding to the CRC-6 bit position in the output data stream is generated by the Frame Generator.
= 1: The framing bit corresponding to the CRC-6 bit position in the input data stream on the TSDn/MTSD pin will be output transparently.
This bit is valid when the UF (b6, T1/J1-046H) and the FDIS (b3, T1/J1-006H) are logic 0.
= 0: The framing bit corresponding to the data link bit position in the output data stream is generated by the Frame Generator.
= 1: The framing bit corresponding to the data link bit position in the input data stream on the TSDn/MTSD pin will be output transparently.
FRESH
R/W
7
0
Reserved
6
SIGAEN
R/W
5
0
Reserved
4
214
FDIS
R/W
3
0
FBITBYP
R/W
2
0
T1 / E1 / J1 OCTAL FRAMER
CRCBYP
R/W
1
0
March 5, 2009
FDLBYP
R/W
0
0