IDT82V2108PXG IDT, Integrated Device Technology Inc, IDT82V2108PXG Datasheet - Page 86

• Manufacturer Part Number: IDT82V2108PXG
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG

IDT82V2108
3.13.2.4
the previous frame and the result is input into the F-bit on the TSDn/
MTSD and TSSIGn/MTSSIG pins. The even parity or odd parity is cho-
sen by the TPTYP (b7, T1/J1-002H) and whether the F-bit is calculated
or not is determined by the PTY_EXTD (b3, T1/J1-002H). The parity
error event on the TSDn pin will be captured by the TSDI (b5, T1/J1-
002H) and the parity error event on the TSSIGn pin will be captured by
the TSSIGI (b4, T1/J1-002H). The TSDI (b5, T1/J1-002H) and TSSIGI
(b4, T1/J1-002H) will be cleared after being read. The parity error will
cause an interrupt on the INT pin if the TPRTYE (b6, T1/J1-002H) is
enabled.
3.13.2.5
T1/J1 mode E1 rate mode) or 8.192MHz (in Transmit Multiplexed
mode), the channel offset and/or bit offset between TSCFS/MTSCFS
and the start of the corresponding frame on TSDn/MTSD can be config-
ured. The channel offset and bit offset can be set in both single clock
mode (CMS [b5, T1/J1-015H] = 0) and double clock mode (CMS [b5, T1/
J1-015H] = 1).
TSOFF[6:0] (b6~0, T1/J1-014H). The TSOFF[6:0] (b6~0, T1/J1-014H)
give a binary representation.
BOFF[2:0] (b2~0, T1/J1-015H). The bit offset value equals the setting in
the BOFF[2:0] (b2~0, T1/J1-015H). That is, ‘000’ in the BOFF[2:0]
(b2~0, T1/J1-015H) means no bit offset; ‘001’ in the BOFF[2:0] (b2~0,
T1/J1-015H) means one bit offset, and so on (refer to the examples in
Functional Description
MTSCCKB
MTSCFS
MTSSIG
MTSD
LTDn
LTCKn
In the above four modes, parity check is calculated over the bits in
When the system clock rate is 2.048MHz (in Transmit Clock Slave
The channel offset is enabled by setting a non-zero value into the
The bit offset is enabled by setting a non-zero value into the
Line Interface (of any of the Framer1 to Framer4). LTCK is 1.544M:
8
D
Parity
bit
P
P
Parity Check
Offset
X
X
X
X
Framer1
X
X
X
CH24-7
X
Figure 62. T1/J1 Transmit Multiplexed Mode - Functional Timing Example 2
X
X
X
X
F-bit
F
X
Parity
bit
P
P
CH24-8
X
X
The TSOFF[6:0] of Framer1 are set to 7'b0000000, the TSOFF[6:0] of Framer2 are set to 7'b0000001,
the TSOFF[6:0] of Framer3 are set to 7'b0000010, the TSOFF[6:0] of Framer4 are set to 7'b0000011,
In this example, Framer1 to Framer4 are supposed to be demultiplexed from one multiplexed bus.
X
X
Framer2
The CMS (b5, T1/J1-015H) is logic 1, i.e., the bankplane clock rate is 16.384Mbit/s.
X
X
X
X
X
X
X
X
F-bit
the BOFF of the four Framers are set to logic 0:
F-bit
The TSCCKBFALL (b3, T1/J1-004H) is logic 0.
F
X
Parity
bit
P
P
X
X
X
X
CH1-1
Framer3
X
X
76
X
X
Figure 63 and Figure 64). When the bit offset is configured, the signal on
TSSIGn/MTSSIG or the pulse on TSFSn is aligned to RSDn/MRSD.
X
X
X
X
F-bit
F
X
Parity
bit
P
P
CH1-2
X
X
X
X
Framer4
X
X
X
X
X
X
CH1-3
X
X
F-bit
F
X
X
1
T1 / E1 / J1 OCTAL FRAMER
2
X
3
X
CH1-4
Framer1_CH1
X
4
A
5
B
6
March 5, 2009
7
C
CH1-5
D
8