DSPIC33FJ128MC706-I/PT Microchip Technology Inc., DSPIC33FJ128MC706-I/PT Datasheet - Page 145
DSPIC33FJ128MC706-I/PT
Manufacturer Part Number
DSPIC33FJ128MC706-I/PT
Description
16 BIT MCU/DSP 64LD 40MIPS 128KB FLASH
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC33FJ128MC706-IPT.pdf
(371 pages)
Specifications of DSPIC33FJ128MC706-I/PT
A/d Inputs
16-Channels, 12-Bit
Comparators
8
Cpu Speed
40 MIPS
Eeprom Memory
0 Bytes
Input Output
53
Interface
CAN/I2C/SPI/UART
Ios
53
Memory Type
Flash
Number Of Bits
16
Package Type
64-pin TQFP
Programmable Memory
128K Bytes
Ram Size
16K Bytes
Timers
9-16-bit, 4-32-bit
Voltage, Range
3-3.6
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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DSPIC33FJ128MC706-I/PT
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REGISTER 7-5:
REGISTER 7-6:
© 2006 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
Note 1:
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-10
bit 9-0
Note 1:
R/W-0
R/W-0
R/W-0
U-0
—
2:
If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
Number of DMA transfers = CNT<9:0> + 1.
PAD<15:0>: Peripheral Address Register bits
Unimplemented: Read as ‘0’
CNT<9:0>: DMA Transfer Count Register bits
R/W-0
R/W-0
R/W-0
U-0
—
DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER
DMAxCNT: DMA CHANNEL x TRANSFER COUNT REGISTER
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
U-0
Preliminary
—
PAD<15:8>
CNT<7:0>
PAD<7:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2)
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
x = Bit is unknown
x = Bit is unknown
dsPIC33F
R/W-0
R/W-0
R/W-0
U-0
(1)
—
DS70165D-page 143
(1)
CNT<9:8>
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
bit 0
bit 8
bit 0
(2)
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