DSPIC33FJ128MC706-I/PT Microchip Technology Inc., DSPIC33FJ128MC706-I/PT Datasheet - Page 267

• Manufacturer Part Number: DSPIC33FJ128MC706-I/PT
• Description: 16 BIT MCU/DSP 64LD 40MIPS 128KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ128MC706-I/PT

• A/d Inputs: 16-Channels, 12-Bit
• Comparators: 8
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: CAN/I2C/SPI/UART
• Ios: 53
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 16K Bytes
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

21.3.7
The DCI module has a dedicated 12-bit time base that
produces the bit clock. The bit clock rate (period) is set
by writing a non-zero 12-bit value to the BCG<11:0>
control bits in the DCICON3 SFR.
When the BCG<11:0> bits are set to zero, the bit clock
will be disabled. If the BCG<11:0> bits are set to a non-
zero value, the bit clock generator is enabled. These
bits should be set to ‘0’ and the CSCKD bit set to ‘1’ if
the serial clock for the DCI is received from an external
device.
The formula for the bit clock frequency is given in
Equation 21-2.
TABLE 21-1:
© 2006 Microchip Technology Inc.
Note 1:
F
S
44.1
2:
12
32
48
(kHz)
8
When the CSCK signal is applied externally (CSCKD = 1), the external clock high and low times must
meet the device timing requirements.
When the CSCK signal is applied externally (CSCKD = 1), the BCG<11:0> bits have no effect on the
operation of the DCI module.
BIT CLOCK GENERATOR
DEVICE FREQUENCIES FOR COMMON CODEC CSCK FREQUENCIES
F
CSCK
256
256
32
32
64
/F
S
F
CSCK
1.4112
2.048
3.072
1.024
3.072
(MHz)
(1)
Preliminary
F
OSC
5.6448
8.192
6.144
8.192
6.144
(MH
EQUATION 21-2:
The required bit clock frequency will be determined by
the system sampling rate and frame size. Typical bit
clock frequencies range from 16x to 512x the converter
sample rate depending on the data converter and the
communication protocol that is used.
To achieve bit clock frequencies associated with com-
mon audio sampling rates, the user will need to select
a crystal frequency that has an ‘even’ binary value.
Examples of such crystal frequencies are listed in
Table 21-1.
Z
)
PLL
F
16
BCK
4
8
8
8
=
BIT CLOCK FREQUENCY
2 (BCG + 1)
•
F
dsPIC33F
F
CY
CY
11.2896
12.288
16.384
24.576
8.192
(MIPS)
DS70165D-page 265
BCG
1
1
7
3
3
(2)