DSPIC33FJ128MC706-I/PT Microchip Technology Inc., DSPIC33FJ128MC706-I/PT Datasheet - Page 4

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DSPIC33FJ128MC706-I/PT

Manufacturer Part Number
DSPIC33FJ128MC706-I/PT
Description
16 BIT MCU/DSP 64LD 40MIPS 128KB FLASH
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet

Specifications of DSPIC33FJ128MC706-I/PT

A/d Inputs
16-Channels, 12-Bit
Comparators
8
Cpu Speed
40 MIPS
Eeprom Memory
0 Bytes
Input Output
53
Interface
CAN/I2C/SPI/UART
Ios
53
Memory Type
Flash
Number Of Bits
16
Package Type
64-pin TQFP
Programmable Memory
128K Bytes
Ram Size
16K Bytes
Timers
9-16-bit, 4-32-bit
Voltage, Range
3-3.6
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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dsPIC33F
Communication Modules:
• 3-wire SPI (up to 2 modules):
• I
• UART (up to 2 modules):
• Data Converter Interface (DCI) module:
• Enhanced CAN (ECAN™ module) 2.0B active
DS70165D-page 2
- Framing supports I/O interface to simple
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
- Interrupt on address bit detect
- Interrupt on UART error
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN bus support
- IrDA
- High-Speed Baud mode
- Hardware Flow Control with CTS and RTS
- Codec interface
- Supports I
- Up to 16-bit data words, up to 16 words per
- 4-word deep TX and RX buffers
(up to 2 modules):
- Up to 8 transmit and up to 32 receive buffers
- 16 receive filters and 3 masks
- Loopback, Listen Only and Listen All
- Wake-up on CAN message
- Automatic processing of Remote
- FIFO mode using DMA
- DeviceNet™ addressing support
2
C™ (up to 2 modules):
codecs
sampling modes
frame
Messages modes for diagnostics and bus
monitoring
Transmission Requests
®
encoding and decoding in hardware
2
S and AC’97 protocols
Preliminary
Motor Control Peripherals:
• Motor Control PWM (up to 8 channels):
• Quadrature Encoder Interface module:
Analog-to-Digital Converters (ADCs):
• Up to two ADC modules in a device
• 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:
CMOS Flash Technology:
• Low-power, high-speed Flash technology
• Fully static design
• 3.3V (±10%) operating voltage
• Industrial temperature
• Low-power consumption
Packaging:
• 100-pin TQFP (14x14x1 mm and 12x12x1 mm)
• 80-pin TQFP (12x12x1 mm)
• 64-pin TQFP (10x10x1 mm)
- 4 duty cycle generators
- Independent or Complementary mode
- Programmable dead time and output polarity
- Edge or center-aligned
- Manual output override control
- Up to 2 Fault inputs
- Trigger for ADC conversions
- PWM frequency for 16-bit resolution
- PWM frequency for 11-bit resolution
- Phase A, Phase B and index pulse input
- 16-bit up/down position counter
- Count direction status
- Position Measurement (x2 and x4) mode
- Programmable digital noise filters on inputs
- Alternate 16-bit Timer/Counter mode
- Interrupt on position counter rollover/underflow
- 2, 4 or 8 simultaneous samples
- Up to 32 input channels with auto-scanning
- Conversion start can be manual or
- Conversion possible in Sleep mode
- ±2 LSb max integral nonlinearity
- ±1 LSb max differential nonlinearity
Note:
(@ 40 MIPS) = 1220 Hz for Edge-Aligned
mode, 610 Hz for Center-Aligned mode
(@ 40 MIPS) = 39.1 kHz for Edge-Aligned
mode, 19.55 kHz for Center-Aligned mode
synchronized with 1 of 4 trigger sources
See the device variant tables for exact
peripheral features per device.
© 2006 Microchip Technology Inc.

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