DSPIC33FJ128MC706-I/PT Microchip Technology Inc., DSPIC33FJ128MC706-I/PT Datasheet - Page 236

• Manufacturer Part Number: DSPIC33FJ128MC706-I/PT
• Description: 16 BIT MCU/DSP 64LD 40MIPS 128KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ128MC706-I/PT

• A/d Inputs: 16-Channels, 12-Bit
• Comparators: 8
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: CAN/I2C/SPI/UART
• Ios: 53
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 16K Bytes
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

dsPIC33F
An additional buffer is always committed to monitoring
the bus for incoming messages. This buffer is called
the Message Assembly Buffer (MAB).
All messages are assembled by the MAB and are trans-
ferred to the buffers only if the acceptance filter criterion
are met. When a message is received, the RBIF flag
(CiINTF<1>) will be set. The user would then need to
inspect the CiVEC and/or CiRXFUL1 register to deter-
mine which filter and buffer caused the interrupt to get
generated. The RBIF bit can only be set by the module
when a message is received. The bit is cleared by the
user when it has completed processing the message in
the buffer. If the RBIE bit is set, an interrupt will be
generated when a message is received.
20.4.2
The ECAN module provides FIFO buffer functionality if
the buffer pointer for a filter has a value of ‘1111’. In this
mode, the results of a hit on that buffer will write to the
next available buffer location within the FIFO.
The CiFCTRL register defines the size of the FIFO. The
FSA<4:0> bits in this register define the start of the
FIFO buffers. The end of the FIFO is defined by the
DMABS<2:0> bits if DMA is enabled. Thus, FIFO sizes
up to 32 buffers are supported.
20.4.3
The message acceptance filters and masks are used to
determine if a message in the message assembly
buffer should be loaded into either of the receive buff-
ers. Once a valid message has been received into the
Message Assembly Buffer (MAB), the identifier fields of
the message are compared to the filter values. If there
is a match, that message will be loaded into the
appropriate receive buffer. Each filter is associated with
a buffer pointer (FnBP<3:0>), which is used to link the
filter to one of 16 receive buffers.
The acceptance filter looks at incoming messages for
the IDE bit (CiTRBnSID<0>) to determine how to com-
pare the identifiers. If the IDE bit is clear, the message
is a standard frame and only filters with the EXIDE bit
(CiRXFnSID<3>) clear are compared. If the IDE bit is
set, the message is an extended frame, and only filters
with the EXIDE bit set are compared.
20.4.4
The mask bits essentially determine which bits to apply
the filter to. If any mask bit is set to a zero, then that bit
will automatically be accepted regardless of the filter
bit. There are three programmable acceptance filter
masks associated with the receive buffers. Any of
these three masks can be linked to each filter by select-
ing the desired mask in the FnMSK<1:0> bits in the
appropriate CiFMSKSELn register.
DS70165D-page 234
FIFO BUFFER MODE
MESSAGE ACCEPTANCE FILTERS
MESSAGE ACCEPTANCE FILTER
MASKS
Preliminary
20.4.5
The CAN module will detect the following receive
errors:
• Cyclic Redundancy Check (CRC) Error
• Bit Stuffing Error
• Invalid Message Receive Error
These receive errors do not generate an interrupt.
However, the receive error counter is incremented by
one in case one of these errors occur. The RXWAR bit
(CiINTF<9>) indicates that the receive error counter
has reached the CPU warning limit of 96 and an
interrupt is generated.
20.4.6
Receive interrupts can be divided into 3 major groups,
each including various conditions that generate
interrupts:
• Receive Interrupt:
• Wake-up Interrupt:
• Receive Error Interrupts:
- Invalid Message Received:
- Receiver Overrun:
- Receiver Warning:
- Receiver Error Passive:
A message has been successfully received and
loaded into one of the receive buffers. This inter-
rupt is activated immediately after receiving the
End-of-Frame (EOF) field. Reading the RXnIF flag
will indicate which receive buffer caused the
interrupt.
The CAN module has woken up from Disable
mode or the device has woken up from Sleep
mode.
A receive error interrupt will be indicated by the
ERRIF bit. This bit shows that an error condition
occurred. The source of the error can be deter-
mined by checking the bits in the CAN Interrupt
Flag register, CiINTF.
If any type of error occurred during reception of
the last message, an error will be indicated by
the IVRIF bit.
The RBOVIF bit (CiINTF<2>) indicates that an
overrun condition occurred.
The RXWAR bit indicates that the receive error
counter (RERRCNT<7:0>) has reached the
warning limit of 96.
The RXEP bit indicates that the receive error
counter has exceeded the error passive limit of
127 and the module has gone into error passive
state.
RECEIVE ERRORS
RECEIVE INTERRUPTS
© 2006 Microchip Technology Inc.