DSPIC33FJ128MC706-I/PT Microchip Technology Inc., DSPIC33FJ128MC706-I/PT Datasheet - Page 362

• Manufacturer Part Number: DSPIC33FJ128MC706-I/PT
• Description: 16 BIT MCU/DSP 64LD 40MIPS 128KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ128MC706-I/PT

• A/d Inputs: 16-Channels, 12-Bit
• Comparators: 8
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: CAN/I2C/SPI/UART
• Ios: 53
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 16K Bytes
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

INDEX
A
A/D Converter ................................................................... 275
AC Characteristics ............................................................ 316
AC-Link Mode Operation .................................................. 268
ADC Module
Alternate Vector Table (AIVT) ............................................. 87
Arithmetic Logic Unit (ALU)................................................. 33
Assembler
Automatic Clock Stretch.................................................... 215
B
Barrel Shifter ....................................................................... 37
Bit-Reversed Addressing .................................................... 70
Block Diagrams
C
C Compilers
Clock Switching................................................................. 156
Code Examples
© 2006 Microchip Technology Inc.
DMA .......................................................................... 275
Initialization ............................................................... 275
Key Features............................................................. 275
Internal RC Accuracy ................................................ 318
Load Conditions ........................................................ 316
16-bit Mode ............................................................... 268
20-bit Mode ............................................................... 269
ADC11 Register Map .................................................. 55
ADC2 Register Map .................................................... 55
MPASM Assembler................................................... 306
Receive Mode ........................................................... 215
Transmit Mode .......................................................... 215
Example ...................................................................... 71
Implementation ........................................................... 70
Sequence Table (16-Entry)......................................... 71
16-bit Timer1 Module ................................................ 161
A/D Module ....................................................... 276, 277
Connections for On-Chip Voltage Regulator............. 293
DCI Module ............................................................... 261
Device Clock ..................................................... 149, 151
DSP Engine ................................................................ 34
dsPIC33F .................................................................... 24
dsPIC33F CPU Core................................................... 28
ECAN Module ........................................................... 231
Input Capture ............................................................ 169
Output Compare ....................................................... 173
PLL............................................................................ 151
PWM Module ............................................................ 176
Quadrature Encoder Interface .................................. 197
Reset System.............................................................. 83
Shared Port Structure ............................................... 159
SPI ............................................................................ 206
Timer2 (16-bit) .......................................................... 165
Timer2/3 (32-bit) ....................................................... 164
UART ........................................................................ 223
Watchdog Timer (WDT) ............................................ 294
MPLAB C18 .............................................................. 306
MPLAB C30 .............................................................. 306
Enabling .................................................................... 156
Sequence.................................................................. 156
DMA Sample Initialization Method ............................ 139
Erasing a Program Memory Page............................... 80
Initiating a Programming Sequence............................ 81
Loading Write Buffers ................................................. 81
Preliminary
Code Protection ........................................................ 289, 295
Configuration Bits ............................................................. 289
Configuration Register Map .............................................. 289
Configuring Analog Port Pins............................................ 160
CPU
CPU Clocking System ...................................................... 150
Customer Change Notification Service............................. 365
Customer Notification Service .......................................... 365
Customer Support............................................................. 365
D
Data Accumulators and Adder/Subtractor .......................... 35
Data Address Space........................................................... 41
Data Converter Interface (DCI) Module ............................ 261
DC Characteristics............................................................ 310
DCI
Port Write/Read ........................................................ 160
PWRSAV Instruction Syntax .................................... 157
Description (Table) ................................................... 290
Control Register.......................................................... 30
Options ..................................................................... 150
Selection................................................................... 150
Data Space Write Saturation ...................................... 37
Overflow and Saturation ............................................. 35
Round Logic ............................................................... 36
Write Back .................................................................. 36
Alignment.................................................................... 41
Memory Map for dsPIC33F Devices with
Memory Map for dsPIC33F Devices with
Memory Map for dsPIC33F Devices with
Near Data Space ........................................................ 41
Software Stack ........................................................... 67
Width .......................................................................... 41
I/O Pin Input Specifications ...................................... 314
I/O Pin Output Specifications.................................... 315
Idle Current (I
Idle Current (I
Operating Current (I
Power-Down Current (I
Program Memory...................................................... 315
Temperature and Voltage Specifications.................. 310
Bit Clock Generator .................................................. 265
Buffer Alignment with Data Frames.......................... 267
Buffer Control ........................................................... 261
Buffer Data Alignment .............................................. 261
Buffer Length Control ............................................... 267
CSDO Mode Bit ........................................................ 268
Data Justification Control Bit .................................... 266
Device Frequencies for Common Codec
Digital Loopback Mode ............................................. 268
Frame Sync Generator ............................................. 263
Frame Sync Mode Control Bits................................. 263
Interrupts .................................................................. 268
Introduction............................................................... 261
Master Frame Sync Operation ................................. 263
Module Enable.......................................................... 263
Operation.................................................................. 263
Operation During CPU Idle Mode............................. 268
Operation During CPU Sleep Mode ......................... 268
Receive Slot Enable Bits .......................................... 266
16 KBs RAM ....................................................... 43
30 KBs RAM ....................................................... 44
8 KBs RAM ......................................................... 42
CSCK Frequencies (Table) .............................. 265
DOZE
IDLE
) .................................................... 312
) .................................................. 313
DD
) ............................................ 311
PD
)........................................ 312
dsPIC33F
DS70165D-page 359