DSPIC33FJ128MC706-I/PT Microchip Technology Inc., DSPIC33FJ128MC706-I/PT Datasheet - Page 237

• Manufacturer Part Number: DSPIC33FJ128MC706-I/PT
• Description: 16 BIT MCU/DSP 64LD 40MIPS 128KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ128MC706-I/PT

• A/d Inputs: 16-Channels, 12-Bit
• Comparators: 8
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: CAN/I2C/SPI/UART
• Ios: 53
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 16K Bytes
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

20.5
20.5.1
The CAN module has up to eight transmit buffers,
located in DMA RAM. These 8 buffers need to be con-
figured as transmit buffers by setting the corresponding
TX/RX buffer selection (TXENn or TXENm) bit in a
CiTRmnCON register. The overall size of the CAN
buffer area in DMA RAM is selectable by the user and
is
(CiFCTRL<15:13>).
Each transmit buffer occupies 16 bytes of data. Eight of
the bytes are the maximum 8 bytes of the transmitted
message. Five bytes hold the standard and extended
identifiers and other message arbitration information.
The last byte is unused.
20.5.2
Transmit priority is a prioritization within each node of
the pending transmittable messages. There are four
levels of transmit priority. If the TXnPRI<1:0> bits (in
set to ‘11’, that buffer has the highest priority. If the
TXnPRI<1:0> bits for a particular message buffer
are set to ‘10’ or ‘01’, that buffer has an intermediate
priority. If the TXnPRI<1:0> bits for a particular
message buffer are ‘00’, that buffer has the lowest pri-
ority. If two or more pending messages have the same
priority, the messages are transmitted in decreasing
order of buffer index.
20.5.3
To initiate transmission of the message, the TXREQn bit
(in CiTRmnCON) must be set. The CAN bus module
resolves any timing conflicts between the setting of the
TXREQn bit and the Start-of-Frame (SOF), ensuring that
if the priority was changed, it is resolved correctly before
the SOF occurs. When TXREQn is set, the TXABTn,
TXLARBn and TXERRn flag bits are automatically
cleared.
Setting the TXREQn bit simply flags a message buffer
as enqueued for transmission. When the module
detects an available bus, it begins transmitting the
message which has been determined to have the
highest priority.
If the transmission completes successfully on the first
attempt, the TXREQn bit is cleared automatically and
an interrupt is generated if TXnIE was set.
If the message transmission fails, one of the error con-
dition flags will be set and the TXREQn bit will remain
set, indicating that the message is still pending for
transmission. If the message encountered an error
condition during the transmission attempt, the TXERRn
bit will be set and the error condition may cause an
interrupt. If the message loses arbitration during the
transmission attempt, the TXLARBn bit is set. No
interrupt is generated to signal the loss of arbitration.
© 2006 Microchip Technology Inc.
CiTRmnCON) for a particular message buffer are
defined
Message Transmission
TRANSMIT BUFFERS
TRANSMIT MESSAGE PRIORITY
TRANSMISSION SEQUENCE
by
the
DMABS<2:0>
Preliminary
bits
20.5.4
If the RTRENn bit (in the CiTRmnCON register) for a
particular transmit buffer is set, the hardware automat-
ically transmits the data in that buffer in response to
remote transmission requests matching the filter that
points to that particular buffer. The user does not need
to manually initiate a transmission in this case.
20.5.5
The system can also abort a message by clearing the
TXREQ bit associated with each message buffer. Set-
ting the ABAT bit (CiCTRL1<12>) will request an abort
of all pending messages. If the message has not yet
started transmission, or if the message started but is
interrupted by loss of arbitration or an error, the abort
will be processed. The abort is indicated when the
module sets the TXABT bit and the TXnIF flag is not
automatically set.
20.5.6
The CAN module will detect the following transmission
errors:
• Acknowledge Error
• Form Error
• Bit Error
These transmission errors will not necessarily generate
an interrupt but are indicated by the transmission error
counter. However, each of these errors will cause the
transmission error counter to be incremented by one.
Once the value of the error counter exceeds the value
of 96, the ERRIF (CiINTF<5>) and the TXWAR bit
(CiINTF<10>) are set. Once the value of the error
counter exceeds the value of 96, an interrupt is
generated and the TXWAR bit in the Interrupt Flag
register is set.
AUTOMATIC PROCESSING OF
REMOTE TRANSMISSION
REQUESTS
ABORTING MESSAGE
TRANSMISSION
TRANSMISSION ERRORS
dsPIC33F
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