DSPIC33FJ128MC706-I/PT Microchip Technology Inc., DSPIC33FJ128MC706-I/PT Datasheet - Page 272

• Manufacturer Part Number: DSPIC33FJ128MC706-I/PT
• Description: 16 BIT MCU/DSP 64LD 40MIPS 128KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ128MC706-I/PT

• A/d Inputs: 16-Channels, 12-Bit
• Comparators: 8
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: CAN/I2C/SPI/UART
• Ios: 53
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 16K Bytes
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

dsPIC33F
REGISTER 21-1:
DS70165D-page 270
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4-2
bit 1-0
DCIEN
UNFM
R/W-0
R/W-0
DCIEN: DCI Module Enable bit
1 = Module is enabled
0 = Module is disabled
Reserved: Read as ‘0’
DCISIDL: DCI Stop in Idle Control bit
1 = Module will halt in CPU Idle mode
0 = Module will continue to operate in CPU Idle mode
Reserved: Read as ‘0’
DLOOP: Digital Loopback Mode Control bit
1 = Digital Loopback mode is enabled. CSDI and CSDO pins internally connected.
0 = Digital Loopback mode is disabled
CSCKD: Sample Clock Direction Control bit
1 = CSCK pin is an input when DCI module is enabled
0 = CSCK pin is an output when DCI module is enabled
CSCKE: Sample Clock Edge Control bit
1 = Data changes on serial clock falling edge, sampled on serial clock rising edge
0 = Data changes on serial clock rising edge, sampled on serial clock falling edge
COFSD: Frame Synchronization Direction Control bit
1 = COFS pin is an input when DCI module is enabled
0 = COFS pin is an output when DCI module is enabled
UNFM: Underflow Mode bit
1 = Transmit last value written to the transmit registers on a transmit underflow
0 = Transmit ‘0’s on a transmit underflow
CSDOM: Serial Data Output Mode bit
1 = CSDO pin will be tri-stated during disabled transmit time slots
0 = CSDO pin drives ‘0’s during disabled transmit time slots
DJST: DCI Data Justification Control bit
1 = Data transmission/reception is begun during the same serial clock cycle as the frame
0 = Data transmission/reception is begun one serial clock cycle after frame synchronization pulse
Reserved: Read as ‘0’
COFSM<1:0>: Frame Sync Mode bits
11 = 20-bit AC-Link mode
10 = 16-bit AC-Link mode
01 = I
00 = Multi-Channel Frame Sync mode
CSDOM
R/W-0
synchronization pulse
U-0
—
2
DCICON1: DCI CONTROL REGISTER 1
S Frame Sync mode
W = Writable bit
‘1’ = Bit is set
DCISIDL
R/W-0
R/W-0
DJST
U-0
U-0
Preliminary
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
DLOOP
R/W-0
U-0
—
CSCKD
R/W-0
U-0
—
© 2006 Microchip Technology Inc.
x = Bit is unknown
CSCKE
R/W-0
R/W-0
COFSM<1:0>
COFSD
R/W-0
R/W-0
bit 8
bit 0