DS26324GNA3+ Maxim Integrated Products, DS26324GNA3+ Datasheet - Page 13

• Manufacturer Part Number: DS26324GNA3+
• Description: IC LIU E1/T1/J1 3.3V 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS26324GNA3+

• Number Of Drivers/receivers: 16/16
• Protocol: LIN
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LOS15/TECLK
LOS16/CLKA
MODESEL
RCLK10
RCLK11
RCLK12
RCLK13
RCLK14
RCLK15
RCLK16
MOTEL
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
RCLK9
LOS10
LOS11
LOS12
LOS13
LOS14
NAME
MCLK
LOS1
LOS2
LOS3
LOS4
LOS5
LOS6
LOS7
LOS8
LOS9
CSB
G13
P10
P13
K14
F12
H12
R14
N15
K15
H15
B10
E11
F10
P14
PIN
L13
M8
M2
D3
G6
D2
G2
R2
R4
R7
K3
K5
P5
E8
E9
F8
E6
T2
B8
A3
B3
J2
tri-state
TYPE
O,
O
I
I
I
I
Receive Clock for Channels 1–16. The receive data (RPOS/RNEG)
is clocked out on the rising edge of RCLK. If a given receiver is in
power-down mode the RCLK is high impedance. Upon an LOS being
detected, the RCLK is switched from the recovered clock to MCLK.
RCLK can be inverted by the RCLKI register.
Master Clock. This is an independent free-running clock that can be
a multiple of 2.048MHz ±50ppm for E1 mode or 1.544MHz ±50ppm
for T1 mode. The clock selection is available by
MPS1, FREQS, and PLLE. A multiple of 2.048MHz can be internal
adapted to 1.544MHz and a multiple of 1.544MHz can be internal
adapted to 2.048MHz.
Loss-of-Signal Output. This output goes high when there is no
transition on the received signal over a specified interval. The output
will go low when there is sufficient ones density in the received signal.
The LOS criteria for assertion and desertion criteria are described in
Section 5.5.6. The LOS outputs can be configured to comply with
T1.231, ITU-T G.775, or ETS 300 233.
T1/E1 Clock (TECLK) (Ball E11 only). This output becomes a T1 or
E1 programmable clock output when enabled by register MC. For T1
or E1 frequency selection, see the
Clock A (CLKA) (Ball F10 only). This output becomes a
programmable clock output when enabled by register MC. For
frequency options, see
Mode Selection. This pin is used to select the control mode of the
DS26324:
Low → Serial Host Mode
High → Parallel Host Mode
Motorola Intel Select. When this pin is low, Motorola mode is
selected. When this pin is high Intel mode is selected.
Chip Select Bar. This signal must be low during all accesses to the
registers.
DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
HOST SELECTION
13 of 120
CCR
register.
FUNCTION
CCR
register.
MC
bits MPS0,