DS26324GNA3+ Maxim Integrated Products, DS26324GNA3+ Datasheet - Page 28

IC LIU E1/T1/J1 3.3V 256-CSBGA

DS26324GNA3+

Manufacturer Part Number
DS26324GNA3+
Description
IC LIU E1/T1/J1 3.3V 256-CSBGA
Manufacturer
Maxim Integrated Products
Type
Line Interface Units (LIUs)r
Datasheet

Specifications of DS26324GNA3+

Number Of Drivers/receivers
16/16
Protocol
LIN
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
256-CSBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
5.5.3 Peak Detector and Slicer
The slicer determines the polarity and presence of the received data. The output of the slicer is sent to the clock
and data recovery circuitry for extraction of data and clock. The slicer has a built-in peak detector for determination
of the slicing threshold.
5.5.4
The DS26324 will report the signal strength at RTIP and RRING in increments described in
bits CnRL3–CnRL0 located in the
5.5.5 Clock and Data Recovery
The resultant E1 or T1 clock derived from the 2.048/1.544 PLL is internally multiplied by 16 via another internal PLL
and fed to the clock recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16
times oversampler, which is used to recover the clock and data. This oversampling technique offers outstanding
performance to meet jitter tolerance specifications.
5.5.6 Loss of Signal
The DS26324 uses both the digital and analog loss-detection method in compliance with the latest ANSI T1.231 for
T1/J1 and ITU-T G.775 or ETS 300 233 for E1 mode of operation.
LOS is detected if the receiver level falls bellow a threshold analog voltage for certain duration. Alternatively, this
can be termed as having received “zeros” for certain duration. The signal level and timing duration are defined in
accordance with the ANSI T1.231, ITU-T G.775, or ETS 300 233 specifications.
The loss detection thresholds are based on cable loss of 18dB for both T1 and E1 modes.
RCLK is replaced by MCLK when the receiver detects a loss of signal. If the AISEL bit is set in the
the
certain number of ones density at a higher signal level than the loss detection level. The loss detection signal level
and loss reset signal level are defined with a hysteresis to prevent the receiver from bouncing between “LOS” and
“no LOS” states.
Table 5-6
Table 5-6. Loss Criteria ANSI T1.231, ITU-T G.775, and ETS 300 233 Specifications
Loss
Detection
Criteria
Loss Reset
Criteria
CRITERIA
IAISEL
Receive Level Indicator
outlines the specifications governing the loss function.
bit is set, the RPOS/RNEG data is replaced by AIS. The loss state is exited when the receiver detects a
No pulses are detected for 175
±75 bits.
Loss is terminated if a duration
of 12.5% ones are detected over
duration of 175 ±75 bits.
Loss is not terminated if 8
consecutive zeros are found if
B8ZS encoding is used. If B8ZS
is not used loss is not
terminated if 100 consecutive
pulses are zero.
T1.231
RSL1–4
registers.
DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
No pulses are detected for
duration of 10 to 255 bit
periods.
The incoming signal has
transitions for duration of 10 to
255 bit periods.
28 of 120
STANDARD
ITU-T G.775
No pulses are detected for a
duration of 2048 bit periods or
1ms.
Loss reset criteria is not
defined.
Table 6-17.
ETS 300 233
GC
via register
register or

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