DS26324GNA3+ Maxim Integrated Products, DS26324GNA3+ Datasheet - Page 18

• Manufacturer Part Number: DS26324GNA3+
• Description: IC LIU E1/T1/J1 3.3V 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS26324GNA3+

• Number Of Drivers/receivers: 16/16
• Protocol: LIN
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 5-3. Serial Port Operation for Read Access with CLKE = 1
5.1.2 Parallel Port Operation
When using the parallel interface on the DS26324 the user has the option for either multiplexed bus operation or
nonmultiplexed bus operation. The ALE pin is pulled high in nonmultiplexed bus operation. The DS26324 can
operate with either Intel or Motorola bus-timing configurations selected by MOTEL pin. This pin being high selects
the Intel mode. The parallel port is only operational if MODESEL pin is pulled high. The following Table lists all the
pins and their functions in the parallel port mode. See the timing diagrams in Section
Table 5-1. Parallel Port Mode Selection and Pin Functions
5.1.3 Interrupt Handling
There are four sets of events that can potentially trigger an Interrupt. The interrupt functions as follows:
•
•
•
MODESEL, MOTEL,
When status changes on an interruptible event, INTB pin will go low if the event is enabled through the
corresponding Interrupt Enable Register. The INTB has to be pulled high externally with a 10kΩ resister for
wired-OR operation. If a wired-OR operation is not required, the INTB pin can be configured to be high when
not active by setting register GISC.INTM.
When an Interrupt occurs the Host Processor has to read the Interrupt Status register to determine the source
of the Interrupt. The read will also clear the Interrupt Status register and this will clear the output INTB pin. The
Interrupt Status register can also be configured as clear on write as per register GISC.CWE. When set to clear
on write, and interrupt status register bit (and the interrupt it generates) will only be cleared on writing a ‘1’ to
it’s bit location in the interrupt status register. This makes is possible to clear interrupts on some bits in a
register without clearing them on all bits.
Subsequently the host processor can read the corresponding Status Register to check the real-time status of
the event.
SDI
SDO
CSB
MUX
100
110
101
111
SCLK
0
(lsb)
1
A1
2
A2
3
Nonmultiplexed Motorola
Multiplexed Motorola
Nonmultiplexed Intel
PARALLEL HOST
A3
Multiplexed Intel
4
INTERFACE
A4
5
A5
6
DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
A6
7
18 of 120
(msb)
X
8
CSB, ACKB, DSB, RWB, ASB, A[5:0], D[7:0], INTB
CSB, RDYB, WRB, RDB, ALE, A[5:0], D[7:0], INTB
CSB, ACKB, DSB, RWB, ASB, AD[7:0], INTB
CSB, RDYB, WRB, RDB, ALE, AD[7:0], INTB
D0
(lsb)
9
D1
ADDRESS, DATA, AND CONTROL
10
D2
11
D3
12
D4
13
9
D5
for more details.
14
D6
15
(msb)
D7
16