DS26324GNA3+ Maxim Integrated Products, DS26324GNA3+ Datasheet - Page 95

• Manufacturer Part Number: DS26324GNA3+
• Description: IC LIU E1/T1/J1 3.3V 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS26324GNA3+

• Number Of Drivers/receivers: 16/16
• Protocol: LIN
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.2 Instruction Register
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the
TAP controller enters the Shift-IR state, the instruction shift register will be connected between TDI and TDO. While
in the Shift-IR state, a rising edge on TCLK with TMS LOW will shift the data one stage towards the serial output at
TDO. A rising edge on TCLK in the Exit1-IR state or the Exit2-IR state with TMS HIGH will move the controller to
the update-IR state. The falling edge of that same TCLK will latch the data in the instruction shift register to the
instruction parallel output. Instructions supported by the DS26324 and its respective operational binary codes are
shown in
Table 7-1. Instruction Codes for IEEE 1149.1 Architecture
7.2.1 EXTEST
This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction
register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all digital output
pins will be driven. The Boundary Scan Register will be connected between TDI and TDO. The Capture-DR will
sample all digital inputs into the Boundary Scan Register.
7.2.2 HIGHZ
All digital outputs of the device will be placed in a high-impedance state. The Bypass Register will be connected
between TDI and TDO.
7.2.3 CLAMP
All digital outputs of the device will output data from the boundary scan parallel output while connecting the Bypass
Register between TDI and TDO. The outputs will not change during the CLAMP instruction.
7.2.4 SAMPLE/PRELOAD
This is a mandatory instruction for the IEEE 1149.1 specification that supports two functions. The digital I/Os of the
device can be sampled at the Boundary Scan Register without interfering with the normal operation of the device
by using the Capture-DR state. SAMPLE/PRELOAD also allows the device to shift data into the Boundary Scan
Register via TDI using the Shift-DR state.
7.2.5 IDCODE
When the IDCODE instruction is latched into the Parallel Instruction Register, the Identification Test Register is
selected. The device identification code will be loaded into the Identification Register on the rising edge of TCLK
following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via TDO.
During Test-Logic-Reset, the identification code is forced into the Instruction Register’s parallel output. The ID code
will always have a 1 in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and number
of continuation bytes followed by 16 bits for the device and 4 bits for the version
device ID code for the DS26324.
7.2.6 BYPASS
When the BYPASS instruction is latched into the Parallel Instruction Register, TDI connects to TDO through the
one-bit test Bypass Register. This allows data to pass from TDI to TDO not affecting the device’s normal operation.
SAMPLE/PRELOAD
INSTRUCTION
BYPASS
EXTEST
IDCODE
CLAMP
Table
HIGHZ
7-1.
SELECTED REGISTER
Device Identification
Boundary Scan
Boundary Scan
Bypass
Bypass
Bypass
DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
95 of 120
INSTRUCTION CODES
000
010
011
100
110
111
Table
7-2.
Table 7-3
lists the