DS26324GNA3+ Maxim Integrated Products, DS26324GNA3+ Datasheet - Page 7

• Manufacturer Part Number: DS26324GNA3+
• Description: IC LIU E1/T1/J1 3.3V 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS26324GNA3+

• Number Of Drivers/receivers: 16/16
• Protocol: LIN
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
2 DETAILED DESCRIPTION
The DS26324 is a single-chip, 16-channel, short-haul line interface unit for T1 (1.544Mbps) and E1 (2.048Mbps)
applications. Sixteen independent receivers and transmitters are provided in a single TE-CSBGA package. The
LIUs can be individually selected for T1, J1, or E1 operation. The LIU requires a single master reference clock. This
clock can be either 1.544MHz or 2.048MHz or multiples thereof, and either frequency can be internally adapted for
T1, J1, or E1 mode. Internal impedance matching provided for both transmit and receive paths reduces external
component count. The transmit waveforms are compliant to G.703 and T1.102 specification. The DS26324
provides software-selectable internal transmit termination for 100Ω T1 twisted pair, 110Ω J1 twisted pair, 120Ω E1
twisted pair, and 75Ω E1 coaxial applications. The transmitters have fast high-impedance capability and can be
individually powered down.
The receivers can function with up to an 18dB receive signal attenuation. A monitor gain setting also can be
enabled to provide 14dB and 20dB. The DS26324 can be configured as a 14-channel LIU with Channel 1 and 9
used for nonintrusive monitoring in accordance with G.772. The receivers and transmitters can be programmed into
single or dual-rail mode. AMI or HDB3/B8ZS encoding and decoding is selectable in single-rail mode. A 128-bit
crystal-less on-board jitter attenuator for each LIU can be placed in receive or transmit directions. The jitter
attenuator meets the ETS CTR12/13 ITU-T G.736, G.742, G.823, and AT&T Pub 62411 specifications.
The DS26324 detects and generates AIS in accordance with T1.231, G.775, and ETS 300 233. Loss of signal is
detected in accordance with T1.231, G.775, and ETS 300 233. The DS26324 can perform digital, analog, remote,
and dual loopbacks on individual LIUs. JTAG boundary scan is provided for the digital pins.
The DS26324 can be configured using 8-bit multiplexed or nonmultiplexed Intel or Motorola ports. A 4-pin serial
port selection is also available for configuration and monitoring of the device.
The analog AMI/HDB3 waveform of the E1 line or the AMI/B8ZS waveform of the T1 line is transformer coupled
into the RTIP and RRING pins of the DS26324. The user can terminate the receive line using only internal
termination that requires no external resistors. Or, the user has the option to use partially internal impedance
matching using a common 120Ω external resistor for E1, T1, and J1, and matching the line impedance internally to
obtain 75Ω, 100Ω, 110Ω, or 120Ω termination values. Note that fully internal impedance match requires a 1:1
transformer on the receive line. Partially internal impedance matching supports either a 1:1 or a 1:2 transformer on
the receive line. If a 1:2 transformer is used, the external termination resistor should be 30Ω. The DS26324 drives
the E1 or T1 line from the TTIP and TRING pins by a 1:2 coupling transformer.
The device recovers clock and data from the analog signal and passes it through a selectable jitter attenuator
outputting the received line clock at RCLK and data at RPOS and RNEG.
The DS26324 receivers can recover data and clock for up to 18dB of attenuation of the transmitted signals in T1
mode and 43dB for E1 mode. Receiver 1 can monitor the performance of receivers 2 to 8 or transmitters 2 to 8.
Receiver 9 can monitor the performance of receivers 10 to 16 or transmitters 10 to 16.
The DS26324 contains 16 identical transmitters. Digital transmit data is input at TPOS/TNEG with reference to
TCLK. The data at these pins can be single-rail or dual-rail. This data is processed by waveshaping circuitry and
the line driver to output at TTIP and TRING in accordance with ANSI T1.102 for T1/J1 or G.703 for E1 mask.
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