DS26324GNA3+ Maxim Integrated Products, DS26324GNA3+ Datasheet - Page 19

• Manufacturer Part Number: DS26324GNA3+
• Description: IC LIU E1/T1/J1 3.3V 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS26324GNA3+

• Number Of Drivers/receivers: 16/16
• Protocol: LIN
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
Figure 5-4. Interrupt Handling Flow Diagram
Interrupt Allowed
No
Interrupt Conditon
Exist?
Yes
Read Interrupt Status
Register
Read Corresponding Status
Register (Optional)
Service the Interrupt
5.2 Power-Up and Reset
Internal Power_On_Reset circuitry generates a reset during power-up. All registers are reset to the default values.
Writing to the Software Reset Register generates at least 1µs reset cycle, which has the same effect as the power-
up reset.
The DS26324 can be reset by a low going pulse on the RSTB pin (see
Table
4-1). A reset can also be performed in
software by writing any value to the
SWR
register.
5.3 Master Clock
The DS26324 requires 2.048MHz ±50ppm or 1.544MHz ±50ppm or multiple thereof. The receiver uses the MCLK
as a reference for clock recovery, jitter attenuation and generating RCLK during LOS. The AIS tTransmission uses
MCLK for transmit all ones condition. See register
MC
to set desired incoming frequency. When the PLLE bit is set,
the master clock adapter will generate both 2.048MHz (E1) and 1.544MHz (T1) clocks. If the PLLE bit is clear, both
internal reference clocks will track MCLK.
MCLK or RCLK can also be used to output CLKA on the LOS16 pin. Register
CCR
is used to select the clock
generated for CLKA and the TECLK. Any RCLK can also be selected as an input to the clock generator using this
same register. For a detailed description of selections available see
Figure
5-5.
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