DS26324GNA3+ Maxim Integrated Products, DS26324GNA3+ Datasheet - Page 82

• Manufacturer Part Number: DS26324GNA3+
• Description: IC LIU E1/T1/J1 3.3V 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS26324GNA3+

• Number Of Drivers/receivers: 16/16
• Protocol: LIN
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 5: PLL Clock Select (PCLKS[2:0]). These bits determine the RCLK that is to be used as the input to the
PLL. If an LOS is detect for the channel that RCLK is recovered from, the PLL will switch to MCLK until the LOS is
cleared. When the LOS is cleared RCLK will be used again. See
must be set to ‘01’ or ‘10’ in order for these settings to take effect.
Table 6-20. PLL Clock Select
Bit 4: T1/E1 Clock Select (TECLKS). When this bit is set the T1/E1 clock output is 2.048MHz. When this bit is
reset the T1/E1 clock rate is 1.544MHz
Bits 3 to 0: Clock A Select (CLKA[3:0]). These bits select the output frequency for CLKA pin. See
available frequencies. For best jitter performance, select MCLK as the source for CLKA and input a 2.048MHz
MCLK.
Table 6-21. Clock A Select
PCLKS[2:0]
CLKA[3:0]
000
001
010
011
100
101
110
111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PCLKS2
7
0
MC.PCLKI[1:0]=01
PCLKS1
PLL CLOCK
SELECTED
6
0
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
CLKA (Hz)
16.384M
12.352M
12.288M
2.048M
4.096M
8.192M
1.544M
3.088M
6.176M
1.536M
3.072M
6.144M
128k
256k
32k
64k
CCR
Clock Control
15h
PCLKS0
5
0
MC.PCLKI[1:0]=10
DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
PLL CLOCK
SELECTED
RCLK10
RCLK11
RCLK12
RCLK13
RCLK14
RCLK15
RCLK16
TECLKS
RCLK9
82 of 120
4
0
CLKA3
Table 6-20
3
0
CLKA2
for RCLK selection. MC.PCLKI[1:0]
2
0
CLKA1
1
0
Table 6-21
CLKA0
0
0
for