MC68HC711E9FU

Manufacturer Part NumberMC68HC711E9FU
ManufacturerFreescale Semiconductor
MC68HC711E9FU datasheet
 


Specifications of MC68HC711E9FU

Cpu FamilyHC11Device Core Size8b
Frequency (max)4MHzInterface TypeSCI/SPI
Program Memory TypeEPROMProgram Memory Size12KB
Total Internal Ram Size512Byte# I/os (max)38
Number Of Timers - General Purpose8Operating Supply Voltage (typ)3.3/5V
Operating Supply Voltage (max)5.5VOperating Supply Voltage (min)3V
On-chip Adc8-chx8-bitInstruction Set ArchitectureCISC
Operating Temp Range0C to 70COperating Temperature ClassificationCommercial
MountingSurface MountPin Count64
Package TypePQFPLead Free Status / Rohs StatusNot Compliant
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Chapter 8
Serial Peripheral Interface (SPI)
8.1 Introduction
The serial peripheral interface (SPI), an independent serial communications subsystem, allows the MCU
to communicate synchronously with peripheral devices, such as:
Frequency synthesizers
Liquid crystal display (LCD) drivers
Analog-to-digital (A/D) converter subsystems
Other microprocessors
The SPI is also capable of inter-processor communication in a multiple master system. The SPI system
can be configured as either a master or a slave device. When configured as a master, data transfer rates
can be as high as one-half the E-clock rate (1.5 Mbits per second for a 3-MHz bus frequency). When
configured as a slave, data transfers can be as fast as the E-clock rate (3 Mbits per second for a 3-MHz
bus frequency).
8.2 Functional Description
The central element in the SPI system is the block containing the shift register and the read data buffer.
The system is single buffered in the transmit direction and double buffered in the receive direction. This
means that new data for transmission cannot be written to the shifter until the previous transfer is
complete; however, received data is transferred into a parallel read data buffer so the shifter is free to
accept a second serial character. As long as the first character is read out of the read data buffer before
the next serial character is ready to be transferred, no overrun condition occurs. A single MCU register
address is used for reading data from the read data buffer and for writing data to the shifter.
The SPI status block represents the SPI status functions (transfer complete, write collision, and mode
fault) performed by the serial peripheral status register (SPSR). The SPI control block represents those
functions that control the SPI system through the serial peripheral control register (SPCR).
Refer to
Figure
8-1, which shows the SPI block diagram.
8.3 SPI Transfer Formats
During an SPI transfer, data is simultaneously transmitted and received. A serial clock line synchronizes
shifting and sampling of the information on the two serial data lines. A slave select line allows individual
selection of a slave SPI device; slave devices that are not selected do not interfere with SPI bus activities.
On a master SPI device, the select line can optionally be used to indicate a multiple master bus
contention. Refer to
Figure
8-2.
Freescale Semiconductor
M68HC11E Family Data Sheet, Rev. 5.1
119