MC68HC711E9FU

Manufacturer Part NumberMC68HC711E9FU
ManufacturerFreescale Semiconductor
MC68HC711E9FU datasheet
 

Specifications of MC68HC711E9FU

Cpu FamilyHC11Device Core Size8b
Frequency (max)4MHzInterface TypeSCI/SPI
Program Memory TypeEPROMProgram Memory Size12KB
Total Internal Ram Size512Byte# I/os (max)38
Number Of Timers - General Purpose8Operating Supply Voltage (typ)3.3/5V
Operating Supply Voltage (max)5.5VOperating Supply Voltage (min)3V
On-chip Adc8-chx8-bitInstruction Set ArchitectureCISC
Operating Temp Range0C to 70COperating Temperature ClassificationCommercial
MountingSurface MountPin Count64
Package TypePQFPLead Free Status / Rohs StatusNot Compliant
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Serial Peripheral Interface (SPI)
INTERNAL
MCU CLOCK
DIVIDER
÷2 ÷4 ÷16 ÷32
SELECT
SPI CONTROL
SPI STATUS REGISTER
SPI INTERRUPT
REQUEST
8.4 Clock Phase and Polarity Controls
Software can select one of four combinations of serial clock phase and polarity using two bits in the SPI
control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active
high or active low clock, and has no significant effect on the transfer format. The clock phase (CPHA)
control bit selects one of two different transfer formats. The clock phase and polarity should be identical
for the master SPI device and the communicating slave device. In some cases, the phase and polarity
are changed between transfers to allow a master device to communicate with peripheral slaves having
different requirements.
When CPHA equals 0, the SS line must be negated and reasserted between each successive serial byte.
Also, if the slave writes data to the SPI data register (SPDR) while SS is low, a write collision error results.
When CPHA equals 1, the SS line can remain low between successive transfers.
120
MSB
LSB
8--BIT SHIFT REGISTER
READ DATA BUFFER
CLOCK
CLOCK
LOGIC
MSTR
SPE
SPI CONTROL REGISTER
INTERNAL
DATA BUS
Figure 8-1. SPI Block Diagram
M68HC11E Family Data Sheet, Rev. 5.1
S
MISO
PD2
M
M
MOSI
PD3
S
S
SCK
PD4
M
SS
PD5
Freescale Semiconductor