MC68HC711E9FU Freescale Semiconductor, MC68HC711E9FU Datasheet - Page 78
MC68HC711E9FU
Manufacturer Part Number
MC68HC711E9FU
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68HC711E9FU.pdf
(242 pages)
Specifications of MC68HC711E9FU
Cpu Family
HC11
Device Core Size
8b
Frequency (max)
4MHz
Interface Type
SCI/SPI
Program Memory Type
EPROM
Program Memory Size
12KB
Total Internal Ram Size
512Byte
# I/os (max)
38
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
8-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
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Central Processor Unit (CPU)
Mnemonic
XGDX
XGDY
TSTA
TSTB
TSX
TSY
TXS
TYS
WAI
Cycle
*
**
Operands
dd
ff
hh
ii
jj
kk
ll
mm
rr
Operators
( )
⇐
⇑
⇓
•
+
⊕
∗
:
–
Infinity or until reset occurs
12 cycles are used beginning with the opcode fetch. A wait state is entered which remains in effect for an integer number of MPU E-clock
cycles (n) until an interrupt is recognized. Finally, two additional cycles are used to fetch the appropriate interrupt vector (14 + n total).
= 8-bit direct address ($0000–$00FF) (high byte assumed to be $00)
= 8-bit positive offset $00 (0) to $FF (255) (is added to index)
= High-order byte of 16-bit extended address
= One byte of immediate data
= High-order byte of 16-bit immediate data
= Low-order byte of 16-bit immediate data
= Low-order byte of 16-bit extended address
= 8-bit mask (set bits to be affected)
= Signed relative offset $80 (–128) to $7F (+127)
Contents of register shown inside parentheses
Is transferred to
Is pulled from stack
Is pushed onto stack
Boolean AND
Arithmetic addition symbol except where used as inclusive-OR symbol
in Boolean formula
Exclusive-OR
Multiply
Concatenation
Arithmetic subtraction symbol or negation symbol (two’s complement)
Test A for Zero
Test B for Zero
Transfer Stack
Transfer Stack
Stack Pointer
Stack Pointer
Transfer X to
Transfer Y to
Exchange D
Exchange D
Pointer to X
Pointer to Y
Operation
or Minus
or Minus
Interrupt
Wait for
(offset relative to address following machine code offset byte))
with X
with Y
Stack Regs & WAIT
IX ⇒ D, D ⇒ IX
IY ⇒ D, D ⇒ IY
Description
SP + 1 ⇒ IX
SP + 1 ⇒ IY
IX – 1 ⇒ SP
IY – 1 ⇒ SP
A – 0
B – 0
Table 4-2. Instruction Set (Sheet 7 of 7)
M68HC11E Family Data Sheet, Rev. 5.1
A
B
Addressing
Mode
INH
INH
INH
INH
INH
INH
INH
INH
INH
18
18
18
Opcode
3E
4D
5D
30
30
35
35
8F
8F
Instruction
Operand
—
—
—
—
—
—
—
—
—
Condition Codes
—
0
1
∆
↓
Cycles
Bit not changed
Bit always cleared
Bit always set
Bit cleared or set, depending on operation
Bit can be cleared, cannot become set
**
2
2
3
4
3
4
3
4
—
—
—
—
—
—
—
—
—
S
—
—
—
—
—
—
—
—
—
X
—
—
—
—
—
—
—
—
—
H
Condition Codes
Freescale Semiconductor
—
—
—
—
—
—
—
—
—
I
—
—
—
—
—
—
—
N
∆
∆
—
—
—
—
—
—
—
Z
∆
∆
—
—
—
—
—
—
—
V
0
0
—
—
—
—
—
—
—
C
0
0
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